//
//  Copyright(C) Renesas Technology Corp. 2002-2005. All rights reserved.
//
//  header file for ITS-DS7 Ver.1.0.0
//
//  FILE      : ITS_DS7.h
//  CREATED   : 2002.04.25
//  MODIFIED  : 2005.06.09
//  AUTHOR    : Renesas Technology Corp.
//  HARDWARE  : RENESAS ITS-DS7
//  HISTORY   : 
//              2003.06.20
//              - Created release code.
//               (based on RENESAS ITS-DS4 Source Kit  Ver.1.2.0 for WCE4.2)
//              2004.02.06
//              - Added PCMCIA register.
//              2004.09.01
//              - Created release code for WCE5.0.
//              2005.02.03
//              - Supported PCCARD driver.
//              2005.06.09
//              - Modified memory mapping for Multiple XIP.

// define for ITS_DS7_SETTING

#define ITS_DS7_COREONLY				1
#define ITS_DS7_COREFUNCTION			2

//#define REG_ACCESS_WAIT
#define REG_ACCESS_NORMAL
//######### P=50MHz ###########################################
#define USEC_TO_CLOCK_LOW       0x80000000
#define USEC_TO_CLOCK_HIGH      0x0000000C
#define CLOCK_TO_USEC_LOW       0x147AE148
#define CLOCK_TO_USEC_HIGH      0x00000000



// Area address offset definitions
#define AREA_0          0x00000000
#define AREA_1          0x04000000
#define AREA_2          0x08000000
#define AREA_3          0x0C000000
#define AREA_4          0x10000000
#define AREA_5          0x14000000
#define AREA_6          0x18000000
#define AREA_7          0xFC000000

#define CACHED_BASE     0x80000000
#define UNCACHED_BASE   0xA0000000


#define DRAM_BASE               (AREA_3 + CACHED_BASE)
#define UNCACHED_DRAM_BASE      (AREA_3 + UNCACHED_BASE)
#define BACKUP_DRAM_BASE        (AREA_2 + CACHED_BASE)
#define UNCACHED_BACKUP_DRAM_BASE (AREA_2 + UNCACHED_BASE)

#define DRV_GLOBAL_OFFSET       0x0012F000
#define DRV_GLOBAL_BASE         (DRV_GLOBAL_OFFSET + UNCACHED_BACKUP_DRAM_BASE)

#define PF_ETHER_OFFSET         0x00180000
#define PF_ETHER_BASE           (AREA_6 + UNCACHED_BASE + PF_ETHER_OFFSET)

#define SYSTEM_FPGA_OFFSET		0x00100000
#define SYSTEM_FPGA_BASE		(AREA_6 + UNCACHED_BASE + SYSTEM_FPGA_OFFSET)

#define SF_SRSTR_OFFSET			0x00000000
#define SF_SNMIR_OFFSET			0x00000010
#define SF_IRQ0SR_OFFSET		0x00000020
#define SF_IRQ0MR_OFFSET		0x00000030
#define SF_MAPSWR_OFFSET		0x00000040
#define SF_FPVERR_OFFSET		0x00000050
#define SF_FPDATER_OFFSET		0x00000060
#define SF_DIPSWMR_OFFSET		0x00001000
#define SF_FPODR_OFFSET			0x00001010
#define SF_ATAESR_OFFSET		0x00001020
#define SF_LED_OFFSET			0x00002000

#define SF_REG_SIZE				0x0100

#define SF_SRSTR				(SYSTEM_FPGA_BASE + SF_SRSTR_OFFSET )
#define SF_CRSTR				(SYSTEM_FPGA_BASE + SF_CRSTR_OFFSET )
#define SF_IRQ0SR				(SYSTEM_FPGA_BASE + SF_IRQ0SR_OFFSET )
#define SF_IRQ0MR				(SYSTEM_FPGA_BASE + SF_IRQ0MR_OFFSET )
#define SF_MAPSWR				(SYSTEM_FPGA_BASE + SF_MAPSWR_OFFSET )
#define SF_FPVERR				(SYSTEM_FPGA_BASE + SF_FPVERR_OFFSET )
#define SF_FPDATER				(SYSTEM_FPGA_BASE + SF_FPDATER_OFFSET )
#define SF_DIPSWMR				(SYSTEM_FPGA_BASE + SF_DIPSWMR_OFFSET )
#define SF_FPODR				(SYSTEM_FPGA_BASE + SF_FPODR_OFFSET )
#define SF_ATAESR				(SYSTEM_FPGA_BASE + SF_ATAESR_OFFSET)
#define SF_LED					(SYSTEM_FPGA_BASE + SF_LED_OFFSET)
#define LED_ALPHA               (SF_LED + 0x70 ) // Top of 8 registers

#define	SF_SRSTR_RESET			0xA5A5			// SYSTEM RESET
#define	SF_IRQ0SR_PCC1			0x0040			// IRQ0 Status (Interrupt of PCC1)
#define	SF_IRQ0SR_PCC0			0x0020			// IRQ0 Status (Interrupt of PCC0)
#define	SF_IRQ0SR_LAN			0x0010			// IRQ0 Status (Interrupt of LAN)
#define	SF_IRQ0SR_200EX			0x0008			// IRQ0 Status (Interrupt of 200PinExCN)
#define	SF_IRQ0SR_SLOT2			0x0004			// IRQ0 Status (Interrupt of SLOT2)
#define	SF_IRQ0SR_SLOT1			0x0002			// IRQ0 Status (Interrupt of SLOT1)
#define	SF_IRQ0SR_SLOT0			0x0001			// IRQ0 Status (Interrupt of SLOT0)
#define	SF_IRQ0MR_PCC1			0x0040			// IRQ0 Status (Interrupt Mask of PCC1)
#define	SF_IRQ0MR_PCC0			0x0020			// IRQ0 Status (Interrupt Mask of PCC0)
#define	SF_IRQ0MR_LAN			0x0010			// IRQ0 Status (Interrupt Mask of LAN)
#define	SF_IRQ0MR_200EX			0x0008			// IRQ0 Status (Interrupt Mask of 200PinExCN)
#define	SF_IRQ0MR_SLOT2			0x0004			// IRQ0 Status (Interrupt Mask of SLOT2)
#define	SF_IRQ0MR_SLOT1			0x0002			// IRQ0 Status (Interrupt Mask of SLOT1)
#define	SF_IRQ0MR_SLOT0			0x0001			// IRQ0 Status (Interrupt Mask of SLOT0)
#define	SF_MAPSWR_EXCS0SEL_SRAM	0x0000			// EXCS0 (SRAM)
#define	SF_MAPSWR_EXCS0SEL_EISA	0x0010			// EXCS0 (EISA)
#define	SF_MAPSWR_CS1SEL_EISA	0x0000			// CS0 (EISA)
#define	SF_MAPSWR_CS1SEL_SRAM	0x0004			// CS0 (SRAM)
#define	SF_MAPSWR_CS1SEL_FLASH0	0x0008			// CS0 (FLASH0)
#define	SF_MAPSWR_CS1SEL_FLASH1	0x000C			// CS0 (FLASH1)
#define	SF_MAPSWR_CS0SEL_EISA	0x0000			// CS0 (EISA)
#define	SF_MAPSWR_CS0SEL_SRAM	0x0001			// CS0 (SRAM)
#define	SF_MAPSWR_CS0SEL_FLASH0	0x0002			// CS0 (FLASH0)
#define	SF_MAPSWR_CS0SEL_FLASH1	0x0003			// CS0 (FLASH1)
#define	SF_ATAESR_ATADASP		0x0001			// ATA Device Connection


#define	BMODE_JUMPTOFLASH_DISABLE	0x80	// SW-2-1 ON  (Flash Image Boot)
#define	BMODE_STATIC_IP				0x40	// SW-2-2 ON  (Static IP address)
#define	BMODE_RAMIMAGE_USE_FLASH	0x20	// SW-2-3 ON  (RamFlash Mode Enable)

// PCMCIA DEFINITIONS
// Memory Map
//  PCMCIA0
//   0x18200000 Attribute Window
//   0x183FFFxx Register Area
//   0x18400000 Common Window
//   0x18500000 I/O Window
//  PCMCIA1
//   0x18600000 Attribute Window
//   0x187FFFxx Register Area
//   0x18800000 Common Window
//   0x18900000 I/O Window

//REGISTER ADDRESS 
#define   PCMCIA_OFFSET				0x00200000
#define   PCCN_OFFSET               0x000FF000
#define   MR_SHPC_BASE              (AREA_6 + UNCACHED_BASE)

#define   PCMCIA_REG_OFFSET			0x00100000
#define   PCMCIA0_BASE				(MR_SHPC_BASE + PCMCIA_OFFSET)
#define   PCMCIA0_REG_BASE          (PCMCIA0_BASE  + PCMCIA_REG_OFFSET + PCCN_OFFSET)

#define   PCMCIA1_BASE				(PCMCIA0_BASE + 0x00400000)
#define   PCMCIA1_REG_BASE          (PCMCIA1_BASE + PCMCIA_REG_OFFSET + PCCN_OFFSET)

#define   PCMCIA_REG_SIZE           0x1000                          //4KB (Page size)

//MEMORY WINDOWS 
#define   PCMCIA_ATTR_WIN_SIZE      0x00040000      //256KB
#define   PCMCIA_ATTR_WIN_OFFSET	0x00000000
#define   PCMCIA0_ATTR_WIN_BASE16   (PCMCIA0_BASE + PCMCIA_ATTR_WIN_OFFSET)
#define   PCMCIA0_ATTR_WIN_BASE8    (PCMCIA0_ATTR_WIN_BASE16 + PCMCIA_ATTR_WIN_SIZE)
#define   PCMCIA1_ATTR_WIN_BASE16	(PCMCIA1_BASE + PCMCIA_ATTR_WIN_OFFSET)
#define   PCMCIA1_ATTR_WIN_BASE8    (PCMCIA1_ATTR_WIN_BASE16 + PCMCIA_ATTR_WIN_SIZE)

#define   PCMCIA_CMN_WIN_SIZE       0x00040000      //256KB
#define   PCMCIA_CMN_WIN_OFFSET		0x00200000
#define   PCMCIA0_CMN_WIN_BASE16    (PCMCIA0_BASE + PCMCIA_CMN_WIN_OFFSET)
#define   PCMCIA0_CMN_WIN_BASE8     (PCMCIA0_CMN_WIN_BASE16 + PCMCIA_CMN_WIN_SIZE)
#define   PCMCIA1_CMN_WIN_BASE16    (PCMCIA1_BASE + PCMCIA_CMN_WIN_OFFSET)
#define   PCMCIA1_CMN_WIN_BASE8     (PCMCIA1_CMN_WIN_BASE16 + PCMCIA_CMN_WIN_SIZE)

#define   PCMCIA_IO_WIN_SIZE        0x00040000      //256KB
#define   PCMCIA_IO_WIN_OFFSET		0x00300000
#define   PCMCIA0_IO_WIN_BASE16     (PCMCIA0_BASE + PCMCIA_IO_WIN_OFFSET)
#define   PCMCIA0_IO_WIN_BASE8      (PCMCIA0_IO_WIN_BASE16 + PCMCIA_IO_WIN_SIZE)
#define   PCMCIA1_IO_WIN_BASE16     (PCMCIA1_BASE + PCMCIA_IO_WIN_OFFSET)
#define   PCMCIA1_IO_WIN_BASE8      (PCMCIA1_IO_WIN_BASE16 + PCMCIA_IO_WIN_SIZE)

#define   PCMCIA_NUM_WINDOWS            6               //2 windows (Real Byte)for each

//1MB Boundaries on the Physical Memory Area (SA)
#define   FIRST_1MB_FROM_BASE0      PCMCIA0_ATTR_WIN_BASE16		//Attribute Memory
#define   SECOND_1MB_FROM_BASE0     PCMCIA0_CMN_WIN_BASE16      //Common Memory
#define   THIRD_1MB_FROM_BASE0      PCMCIA0_IO_WIN_BASE16       //IO Memory
#define   FIRST_1MB_FROM_BASE1      PCMCIA1_ATTR_WIN_BASE16     //Attribute Memory
#define   SECOND_1MB_FROM_BASE1     PCMCIA1_CMN_WIN_BASE16      //Common Memory
#define   THIRD_1MB_FROM_BASE1      PCMCIA1_IO_WIN_BASE16       //IO Memory

//256KB Memory Windows (X)
#define   MR_SHPC_MW0C2_CA          0x00000
#define   MR_SHPC_MW1C2_CA          0x00000
#define   MR_SHPC_IOWC2_CA          0x00000

//Register Offsets
#define   MR_SHPC_MOD_OFFSET    0xFE4
#define   MR_SHPC_OPT_OFFSET    0xFE6
#define   MR_SHPC_CST_OFFSET    0xFE8
#define   MR_SHPC_INTR_OFFSET   0xFEA
#define   MR_SHPC_INTC_OFFSET   0xFEC
#define   MR_SHPC_CPWC_OFFSET   0xFEE
#define   MR_SHPC_MW0C1_OFFSET  0xFF0
#define   MR_SHPC_MW1C1_OFFSET  0xFF2
#define   MR_SHPC_IOWC1_OFFSET  0xFF4
#define   MR_SHPC_MW0C2_OFFSET  0xFF6
#define   MR_SHPC_MW1C2_OFFSET  0xFF8
#define   MR_SHPC_IOWC2_OFFSET  0xFFA
#define   MR_SHPC_CCN_OFFSET    0xFFC
#define   MR_SHPC_CIN_OFFSET    0xFFE

//Definitions of Register Address
/*
#define   MR_SHPC_MOD           (PCMCIA0_REG_BASE + MR_SHPC_MOD_OFFSET)          //Mode Reg.
#define   MR_SHPC_OPT           (PCMCIA0_REG_BASE + MR_SHPC_OPT_OFFSET)          //Option Reg.
#define   MR_SHPC_CST           (PCMCIA0_REG_BASE + MR_SHPC_CST_OFFSET)          //Card Status Reg.
#define   MR_SHPC_INTR          (PCMCIA0_REG_BASE + MR_SHPC_INTR_OFFSET)         //Interrupt Request Reg.
#define   MR_SHPC_INTC          (PCMCIA0_REG_BASE + MR_SHPC_INTC_OFFSET)         //Interrupt Control Reg.
#define   MR_SHPC_CPWC          (PCMCIA0_REG_BASE + MR_SHPC_CPWC_OFFSET)         //Card Power Control Reg.
#define   MR_SHPC_MW0C1         (PCMCIA0_REG_BASE + MR_SHPC_MW0C1_OFFSET)        //Memory Window 0 Conrol Reg. 1
#define   MR_SHPC_MW1C1         (PCMCIA0_REG_BASE + MR_SHPC_MW1C1_OFFSET)        //Memory Window 1 Conrol Reg. 1
#define   MR_SHPC_IOWC1         (PCMCIA0_REG_BASE + MR_SHPC_IOWC1_OFFSET)        //IO Window Conrol Reg. 1
#define   MR_SHPC_MW0C2         (PCMCIA0_REG_BASE + MR_SHPC_MW0C2_OFFSET)        //Memory Window 0 Control Reg. 2