#define   MR_SHPC_MW1C2         (PCMCIA0_REG_BASE + MR_SHPC_MW1C2_OFFSET)        //Memory Window 1 Control Reg. 2
#define   MR_SHPC_IOWC2         (PCMCIA0_REG_BASE + MR_SHPC_IOWC2_OFFSET)        //IO Window Control Reg. 2
#define   MR_SHPC_CCN           (PCMCIA0_REG_BASE + MR_SHPC_CCN_OFFSET)          //Card Control Reg.
#define   MR_SHPC_CIN           (PCMCIA0_REG_BASE + MR_SHPC_CIN_OFFSET)          //PCIC Info Reg.
*/

//MODE REG.
#define   MR_SHPC_MOD_SH4_WAIT  0x0000
#define   MR_SHPC_MOD_SH4_RDY   0x0020              
#define   MR_SHPC_MOD_CKIO_66   0x0010
#define   MR_SHPC_MOD_CKIO_33   0x0000

//OPTION REG. (Test,SPKR Data/Select are not usable)
#define   MR_SHPC_OPT_LED_OUT_0         0x0000
#define   MR_SHPC_OPT_LED_OUT_Z         0x0004
#define   MR_SHPC_OPT_LED_SELECT_BIT2   0x0001
#define   MR_SHPC_OPT_LED_SELECT_CBVD2  0x0000

//CARD STATUS REG.
#define   MR_SHPC_CST_ENDIAN            0x4000
#define   CARD_STATUS(RA)               (((RA)-MR_SHPC_BASE)>>6)    
#define   MR_SHPC_CST_PCIC_RDY_BSY      0x0200
#define   MR_SHPC_CST_VS2               0x0100
#define   MR_SHPC_CST_VS1               0x0080
#define   MR_SHPC_CST_PW_ON             0x0040
#define   MR_SHPC_CST_RDY_BSY           0x0020
#define   MR_SHPC_CST_WPS               0x0010
#define   MR_SHPC_CST_CARD_EMPTY1       0x000c
#define   MR_SHPC_CST_CARD_EMPTY2       0x0008
#define   MR_SHPC_CST_CARD_EMPTY3       0x0004
#define   MR_SHPC_CST_CARD_INSERTED     0x0000
#define   MR_SHPC_CST_CD_MASK           0x000c
#define   MR_SHPC_CST_BAT_GOOD          0x0003
#define   MR_SHPC_CST_BAT_DEAD1         0x0002
#define   MR_SHPC_CST_BAT_WARN          0x0001
#define   MR_SHPC_CST_BAT_DEAD2         0x0000
#define   MR_SHPC_CST_BAT_MASK          0x0003


//INTERRUPT REQUEST REG.
#define   MR_SHPC_INTR_STSCHG           0x0040
#define   MR_SHPC_INTR_IREQ_CHG         0x0020
#define   MR_SHPC_INTR_CARD_PWR         0x0010
#define   MR_SHPC_INTR_CARD_DETECT      0x0008
#define   MR_SHPC_INTR_RDY_CHG          0x0004
#define   MR_SHPC_INTR_BAT_WARN         0x0002
#define   MR_SHPC_INTR_BAT_DEAD         0x0001
#define   MR_SHPC_INTR_BAT_MASK         0x0003

//INTERRUPT CONTROL REG.
#define   MR_SHPC_INTC_LEVEL_IRQ        0x0000
#define   MR_SHPC_INTC_EDGE_IRQ         0x4000  
#define   MR_SHPC_INTC_CARD_IRQ_MASK    0x3800

#define   MR_SHPC_INTC_CARD_IRQ         0x2000
#define   MR_SHPC_INTC_RING_IRQ_MASK    0x0700
#define   MR_SHPC_INTC_RING_IRQ         0x0400
#define   MR_SHPC_INTC_MGT_IRQ          0x0080
#define   MR_SHPC_INTC_MGT_IRQ_MASK     0x00E0

#define   MR_SHPC_INTC_CP_ENABLE        0x0010
#define   MR_SHPC_INTC_DETECT_ENABLE    0x0008
#define   MR_SHPC_INTC_RDY_ENABLE       0x0004
#define   MR_SHPC_INTC_BAT_WARN_ENABLE  0x0002
#define   MR_SHPC_INTC_BAT_DEAD_ENABLE  0x0001

//CARD POWER CONTROL REG.
#define   MR_SHPC_CPWC_CARD_PW_MASK     0x0400      
#define   MR_SHPC_CPWC_CARD_RESET       0x0200
#define   MR_SHPC_CPWC_CARD_PW_DWN      0x0100      //Power Down Mode
#define   MR_SHPC_CPWC_SUSPEND          0x0080      //Power Save Mode
#define   MR_SHPC_CPWC_CARD_ENABLE      0x0040      //Full Power Mode (Maintain)
#define   MR_SHPC_CPWC_AUTO_POWER       0x0020
#define   MR_SHPC_CPWC_VCC_POWER        0x0010
//#define   MR_SHPC_CPWC_VCC_0V         0x000c      //VCC5V and VCC3V are low-active
#define   MR_SHPC_CPWC_VCC_0V           0x0000      //VCC5V and VCC3V are low-active
#define   MR_SHPC_CPWC_VCC_3V           0x0004
#define   MR_SHPC_CPWC_VCC_5V           0x0008                  
#define   MR_SHPC_CPWC_VPP_EQL_VCC      0x0002      //VPP depends upon VCC
#define   MR_SHPC_CPWC_VPP0V            0x0000
#define   MR_SHPC_CPWC_VPP12V           0x0001      //VPP=12V   
#define   MR_SHPC_CPWC_VPP_HI_Z         0x0003      //VPP=Hi-z
        
#define   MR_SHPC_CPWC_VCC_MASK         0xFFF3
#define   MR_SHPC_CPWC_VPP_MASK         0x0003

#define   MR_SHPC_CPWC_BAD_VCC          (MR_SHPC_CPWC_VCC_0V | MR_SHPC_CPWC_VPP0V)
#define   MR_SHPC_CPWC_BAD_VPP          (MR_SHPC_CPWC_VCC_0V | MR_SHPC_CPWC_VPP0V)

//MEMORY WINDOW 0 CONTROL REG.1
#define   MR_SHPC_MW0C1_WINEN           0x8000
#define   MR_SHPC_MW0C1_WIDTH4          0x4000
#define   MR_SHPC_MW0C1_WIDTH3          0x2000
#define   MR_SHPC_MW0C1_WIDTH2          0x1000
#define   MR_SHPC_MW0C1_WIDTH1          0x0800
#define   MR_SHPC_MW0C1_WIDTH0          0x0400
#define   MR_SHPC_MW0C1_HOLD1           0x0200
#define   MR_SHPC_MW0C1_HOLD0           0x0100
#define   MR_SHPC_MW0C1_SETUP1          0x0080
#define   MR_SHPC_MW0C1_SETUP0          0x0040
#define   MR_SHPC_MW0C1_MASK_EXCEPT_SA  0xFFC0
#define   MEM_WIN0_CNTRL1(SA)           ((((SA)- MR_SHPC_BASE) >> 20) & 0x3f)               

//MEMORY WINDOW 1 CONTROL REG.1
#define   MR_SHPC_MW1C1_WINEN           0x8000
#define   MR_SHPC_MW1C1_WIDTH4          0x4000
#define   MR_SHPC_MW1C1_WIDTH3          0x2000
#define   MR_SHPC_MW1C1_WIDTH2          0x1000
#define   MR_SHPC_MW1C1_WIDTH1          0x0800
#define   MR_SHPC_MW1C1_WIDTH0          0x0400
#define   MR_SHPC_MW1C1_HOLD1           0x0200
#define   MR_SHPC_MW1C1_HOLD0           0x0100
#define   MR_SHPC_MW1C1_SETUP1          0x0080
#define   MR_SHPC_MW1C1_SETUP0          0x0040
#define   MEM_WIN1_CNTRL1(SA)           ((((SA)-MR_SHPC_BASE) >> 20) & 0x3f)

//IO WINDOW CONTROL REG.1
#define   MR_SHPC_IOWC1_WINEN           0x8000
#define   MR_SHPC_IOWC1_WIDTH4          0x4000
#define   MR_SHPC_IOWC1_WIDTH3          0x2000
#define   MR_SHPC_IOWC1_WIDTH2          0x1000
#define   MR_SHPC_IOWC1_WIDTH1          0x0800
#define   MR_SHPC_IOWC1_WIDTH0          0x0400
#define   MR_SHPC_IOWC1_HOLD1           0x0200
#define   MR_SHPC_IOWC1_HOLD0           0x0100
#define   MR_SHPC_IOWC1_SETUP1          0x0080
#define   MR_SHPC_IOWC1_SETUP0          0x0040
#define   IO_WIN_CNTRL1(SA)             ((((SA)-MR_SHPC_BASE) >> 20) & 0x3f)


//MEMORY WINDOW 0 CONTROL REG.2
#define  MR_SHPC_MW0C2_SWAP             0x0800
#define  MR_SHPC_MW0C2_WRITE_PRO        0x0400
#define  MR_SHPC_MW0C2_SIZE             0x0200
#define  MR_SHPC_MW0C2_REG              0x0100
#define  MEM_WIN0_CNTRL2(X)             ((((X)>>18) & 0xff)


//MEMORY WINDOW 1 CONTROL REG.2
#define   MR_SHPC_MW1C2_SWAP            0x0800
#define   MR_SHPC_MW1C2_WRITE_PRO       0x0400
#define   MR_SHPC_MW1C2_SIZE            0x0200
#define   MR_SHPC_MW1C2_REG             0x0100
#define   MEM_WIN1_CNTRL2(X)            ((((X)>>18) & 0xff)


//IO WINDOW CONTROL REG.2
#define   MR_SHPC_IOWC2_SWAP            0x0800
#define   MR_SHPC_IOWC2_WRITE_PRO       0x0400
#define   MR_SHPC_IOWC2_SIZE            0x0200
#define   MR_SHPC_IOWC2_AUTO_SIZE       0x0100
#define   IO_WIN_CNTRL2(X)              ((((X)>>18) & 0xff)


//CARD CONTROL REG.
#define   MR_SHPC_CCN_CARD_IO           0x0008  //IO & Memory IF
#define   MR_SHPC_CCN_CARD_MEM          0x0000
#define   MR_SHPC_CCN_LED_ENABLE        0x0004
#define   MR_SHPC_CCN_SPKR_ENABLE       0x0002
#define   MR_SHPC_CCN_INPACK_ENABLE     0x0001

//PCIC INFO REG.
#define   PCIC_ASCLL_S3                 0x5333


#ifdef REG_ACCESS_WAIT
// convenience macros used in every driver
__inline static int RegWait()
{
    int i;
    for( i=0;i<100;i++ );
    return i;
}
#define REG_WAIT    RegWait()
#define READ_REGISTER_ULONG(reg)        (REG_WAIT,(*(volatile unsigned long * const)(reg)))
#define WRITE_REGISTER_ULONG(reg, val)  (REG_WAIT,(*(volatile unsigned long * const)(reg)) = (val))
#define READ_REGISTER_USHORT(reg)       (REG_WAIT,(*(volatile unsigned short * const)(reg)))
#define WRITE_REGISTER_USHORT(reg, val) (REG_WAIT,(*(volatile unsigned short * const)(reg)) = (val))
#define READ_REGISTER_UCHAR(reg)        (REG_WAIT,(*(volatile unsigned char * const)(reg)))
#define WRITE_REGISTER_UCHAR(reg, val)  (REG_WAIT,(*(volatile unsigned char * const)(reg)) = (val))

#endif //REG_ACCESS_WAIT

#ifdef REG_ACCESS_NORMAL

// Macro definitions used to access memory-mapped registers
#define READ_REGISTER_ULONG(reg) \
            (*(volatile unsigned long * const)(reg))
#define WRITE_REGISTER_ULONG(reg, val) \
            (*(volatile unsigned long * const)(reg)) = (val)
#define READ_REGISTER_USHORT(reg) \
            (*(volatile unsigned short * const)(reg))
#define WRITE_REGISTER_USHORT(reg, val) \
            (*(volatile unsigned short * const)(reg)) = (val)
#define READ_REGISTER_UCHAR(reg) \
            (*(volatile unsigned char * const)(reg))
#define WRITE_REGISTER_UCHAR(reg, val) \
            (*(volatile unsigned char * const)(reg)) = (val)
#endif //REG_ACCESS_NORMAL

typedef volatile BYTE   *PVBYTE;
typedef volatile SHORT  *PVSHORT;
typedef volatile USHORT *PVUSHORT;
typedef volatile ULONG  *PVULONG;
typedef volatile DWORD  *PVDWORD;

// Reschedule period in ms, moved from TIMER.H
#define RESCHED_PERIOD      1 // 1ms

// Delay functions
DWORD AdjustMicroSecondsToLoopCount( DWORD dwMicroSeconds );
DWORD BusyWait( DWORD dwLoopCount );

void PrintLED(char *);
void WriteLED(DWORD);