;
;   Copyright(C) Renesas Technology Corp. 1998-2005. All rights reserved.
;
;   Ethernet Boot Loader for ITS-DS7
;
;   FILE      : startup.src
;   CREATED   : 2002.04.25
;   MODIFIED  : 2005.08.01
;   AUTHOR    : Renesas Technology Corp.
;   HARDWARE  : RENESAS ITS-DS7
;   HISTORY   : 
;               2003.06.20
;               - Created release code.
;                 (based on EBOOT for ITS-DS4 Ver.1.2.0 for WCE4.2)
;               2003.11.21
;               - Settings for pin multi registers are changed.
;               2004.01.15
;               - An initialization procedure is changed.
;		        - VBR -> SR -> RTC_clock select -> Pin_multi -> GPIO ->
;                 -> 300ms wait -> CPG_FRQCR -> 200us wait -> BBG_BSC ->
;                 -> MCU_DDRSDRAM -> DDR_PAD -> EBOOT copy to RAM -> 
;                 -> cache -> stack -> call main
;               - reference MiniMonitor v.3.0.0
;               2004.01.21
;               - change register setting order SRDA->STR
;               - reference MiniMonitor v.3.5.1
;               2004.01.26
;               - The CPUOPM register set up was improved.
;               - DDR PAD timing change program for SH7770 2ndcut.The routine was replaced.
;               - reference MiniMonitor v.3.7.1
;               2004.02.05
;               - The WDT overflow manual reset processing was added when FRQCR register setting.
;               - Dummy read processing was added when FRQCR register setting.
;               - reference MiniMonitor v.3.8.2
;               2004.02.12
;               - Modified check aif - aelsif - aelse - aendi.
;               2004.02.19
;               - The FRQCR register setting value was corrected.
;               - reference MiniMonitor v.3.8.3
;               2004.03.04
;               - optimized CSWCR0/CSWCR1/ECSWCR0.
;               - The WDT overflow manual reset processing was changed when FRQCR register setting.
;               - reference MiniMonitor v.3.8.5
;               2004.03.15
;               - Revised AutoRefresh for DDR-SDRAM.
;               - Revised DDR PAD timing change.
;               - Modified CS0CTRL/CSPWCR0/CSPWCR1/ECSPWCR0 set the equivalent MiniMonitor v.3.8.5.
;               - Modified CPG setting.
;               2004.04.09
;               - Modified The setting value of a CPUOPM register was optimized for SH7770-3rdcut.
;               - Modified The DDR-SDRAM initiallize routine was optimized.
;               - Modified The DDR PAD timing change routine was replaced.
;               - reference MiniMonitor v.4.1.0
;               2004.04.12
;               - Modified The FRQCR register setting value was corrected.(Ex-Bus = 50MHz)
;               - Modified It changed so that the 200us soft wait routine(for PLL:CY2309ZC) might be performed by LRAM.
;               - Modified It changed so that the 200us soft wait routine(for DDR) might be performed by LRAM.
;               - reference MiniMonitor v.4.2.0
;               2004.04.20
;               - Modified The FRQCR register setting value was corrected.(Ex-Bus = 50MHz)
;               - Added When watchdog timer was invalid, the routine which displays an error was added.
;               2004.04.22
;               - Modified unify a setting method of a value of DDR-SDRAM in macro-use.
;               - Modified The comment was corrected.
;               2004.04.23
;               - Modified only 2ndcut sets CPUOPM.
;               - Added comment that IRMCR.R1 is set by an initial value before CPUOPM update.
;               2004.06.18
;               - Modified compile warning measures for POOL.
;               2004.07.05
;               - Modified watchdog timer invalid check is 2ndcut later.
;               2005.06.09
;               - Modified memory mapping for Multiple XIP.
;               2005.06.10
;               - Modified memory mapping for Multiple XIP.
;               2005.08.01
;               - Changed Boot Loader Model(used BLCOMMON library).
;                 filename is changed from init.src to startup.src.
;

;++
;
; THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
; ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
; PARTICULAR PURPOSE.
; Copyright (c) 1995, 1996, 1997, 1998  Microsoft Corporation
;
; Module Name:
;
;    init.src
;
; Abstract:
;
;    This module implements the C start-up code for the Windows CE bootloader on
;    the SH-3 based P2 platform.  Since the bootloader's requirements are
;    minimal and the system has not been initialized, the focus is on CPU setup
;    and not full C runtime support.
;
; Functions:
;
;
; Notes: 
;
;--

        .list OFF
        .include "kxshx.h"
        .include "shx.inc"
		.include "platform.inc"
		.include "sh7770.inc"
		.include "drv_glob.inc"
        .include "boot.inc"
        .list ON

Stack:		.equ    h'88137FFC	;check eboot.bib
LRAM_SP		.EQU	H'E5011FF0	;Stack Pointer for ITS-DS7 LRAM

ROMOFFSET:	.equ	h'f000ffff

        .import _main

;************************************************************************************
;*      FUNCTION :              StartUp()
;*      DESCRIPTION :   The initial starting point of the system
;*      INPUTS :                None - we are branched to from the reset vector
;*      OUTPUTS :               None, we branch to the main()
;*      CAUTIONS :              We are operating in Clock Mode 3.  There are a lot
;*                              of things that can change based on the position of
;*                              some DIP Switches so keep up with the comments
;*
;*    o Constructors are not initialized.  They aren't used by the bootloader.
;*
;*    o exit is not called.  There is no stdio library, etc., to close.
;*
;*    The bootloader is configured to run from RAM in memory section P1 (cached)
;*    but the SH-4 boots in FLASH in section P2 (uncached).  Thus, the initial
;*    memory setup code below (up to the call to _main) must be position
;*    independent.
;*
;* Arguments:
;*
;*    None; we are branched to, not called.
;*
;* Return Value:
;*
;*    None; there is nothing to return to.
;*
;*************************************************************************************

        LEAF_ENTRY _StartUp

;-------------------------------------------------------
;
; DEBUG LED
;
;
;    mov.l   #h'53, r2				; 'S'
;    mov.l   #LED_ALPHA, r3
;    mov.b   r2, @r3
;
;    mov.l   #h'54, r2				; 'T'
;    add     #LED_ALPHA_STRIDE, r3
;    mov.b   r2, @r3
;
;    mov.l   #h'41, r2				; 'A'
;    add     #LED_ALPHA_STRIDE, r3
;    mov.b   r2, @r3
;
;    mov.l   #h'52, r2				; 'R'
;    add     #LED_ALPHA_STRIDE, r3
;    mov.b   r2, @r3
;
;    mov.l   #h'54, r2				; 'T'
;    add     #LED_ALPHA_STRIDE, r3
;    mov.b   r2, @r3

;-------------------------------------------------------
;
; First step, setup of SH4R CORE register
;

        mov.l   #VBR_DEFAULT,r0
        ldc     r0,vbr

        mov.l   #TM_SR,r0		; release mask etc
        ldc     r0,sr

;-----------------------------------------------------
;
; Setup RTC CLKSEL -> External Clock
;

        mov.l   #RTC_CLKSEL,r1
        mov.w   #RTC_CLKSEL_EXTERNAL,r0
        mov.w   r0,@r1
        nop

;-----------------------------------------------------
;
; CPU Operation mode Setting for 2nd cut or later
;

      .aif SH7770_REVISION eq SH7770_2NDCUT
		; IRMCR.R1=0(initial value)
		mov.l	#CPUOPM_OFF,r0
		mov.l	#CPUOPM_REG,r1
		mov.l	r0,@r1
      .aendi	;"SH7770_2NDCUT"

;-------------------------------------------------------
;
; Wait for 300ms here was moved to the after GPIO Settings.


;------------------------------------------------------
;
; board setting at its_ds7.bat
;

    .aif ITS_DS7_SETTING eq ITS_DS7_COREONLY

CoreOnlySetting:

;-------------------------------------------------------
;
; Pin Multi Settings
;

		; PMSR1 Setting --------------------------------

		mov.l	#VCRSYS_PMMR, r2

		mov.l	#VCRSYS_PMSR1, r1
		mov.l	#~VCRSYS_PMSR1_COREONLY_DEFAULT, r0
		mov.l	r0, @r2
		mov.l	#VCRSYS_PMSR1_COREONLY_DEFAULT, r0
		mov.l	r0, @r1


		; PMSR2 Setting --------------------------------

		mov.l	#VCRSYS_PMMR, r2

		mov.l	#VCRSYS_PMSR2, r1
		mov.l	#~VCRSYS_PMSR2_COREONLY_DEFAULT, r0
		mov.l	r0, @r2
		mov.l	#VCRSYS_PMSR2_COREONLY_DEFAULT, r0
		mov.l	r0, @r1


		; PMSR3 Setting --------------------------------

		mov.l	#VCRSYS_PMMR, r2

		mov.l	#VCRSYS_PMSR3, r1
		mov.l	#~VCRSYS_PMSR3_COREONLY_DEFAULT, r0
		mov.l	r0, @r2
		mov.l	#VCRSYS_PMSR3_COREONLY_DEFAULT, r0
		mov.l	r0, @r1


		; PMSR4 Setting --------------------------------

		mov.l	#VCRSYS_PMMR, r2

		mov.l	#VCRSYS_PMSR4, r1
		mov.l	#~VCRSYS_PMSR4_COREONLY_DEFAULT, r0
		mov.l	r0, @r2
		mov.l	#VCRSYS_PMSR4_COREONLY_DEFAULT, r0
		mov.l	r0, @r1


		; PMSRG Setting --------------------------------

		mov.l	#VCRSYS_PMMR, r2

		mov.l	#VCRSYS_PMSRG, r1
		mov.l	#~VCRSYS_PMSRG_DEFAULT, r0
		mov.l	r0, @r2
		mov.l	#VCRSYS_PMSRG_DEFAULT, r0
		mov.l	r0, @r1
    
;-------------------------------------------------------
;
; GPIO Initialize

		; All Port is General I/O

		mov.l	#h'00000000, r0
		mov.l	#GPIO_GPIO0_IOINTSEL, r1
		mov.l	r0, @r1

		mov.l	#GPIO_GPIO1_IOINTSEL, r1
		mov.l	r0, @r1

		mov.l	#GPIO_GPIO2_IOINTSEL, r1
		mov.l	r0, @r1

		mov.l	#GPIO_GPIO3_IOINTSEL, r1
		mov.l	r0, @r1

		; GPIO0 Setting

		mov.l	#h'00FFFFFF,r0		;GPIO-0-A0..A23=output
		mov.l	#GPIO_GPIO0_INOUTSEL,r1		;GPIO-0-INOUTSEL
		mov.l	r0,@r1

		; GPIO1 Setting ( ExBus or DataBus)

		; GPIO2 Setting
		mov.l	#h'C0760000,r0		;GPIO-2-31,30,22-20,18,17=output

		mov.l	#GPIO_GPIO2_INOUTSEL,r1		;GPIO-2-INOUTSEL
		mov.l	r0,@r1

		; GPIO3 Setting (A-21,22 Pin multi for TIMER0,1)

		mov.l	#h'20000000,r0		;GPIO-3-29 change to negative logic
		mov.l	#GPIO_GPIO3_POSNEG,r1		;GPIO-3-POSNEG
		mov.l	r0,@r1
	
		mov.l	#h'3FE3FFE8,r0		;GPIO-3-31-21/17-5 = output

		mov.l	#GPIO_GPIO3_INOUTSEL,r1		;GPIO-3-INOUTSEL
		mov.l	r0,@r1

    .aelse	;"ITS_DS7_COREONLY"

CoreFunctionSetting:

;-------------------------------------------------------
;
; Core + Function Board Setting


;-------------------------------------------------------
;
; Pin Multi Settings
;

		; PMSR1 Setting --------------------------------

		mov.l	#VCRSYS_PMMR, r2

		mov.l	#VCRSYS_PMSR1, r1
		mov.l	#~VCRSYS_PMSR1_COREFUNC_DEFAULT, r0
		mov.l	r0, @r2
		mov.l	#VCRSYS_PMSR1_COREFUNC_DEFAULT, r0
		mov.l	r0, @r1


		; PMSR2 Setting --------------------------------

		mov.l	#VCRSYS_PMMR, r2

		mov.l	#VCRSYS_PMSR2, r1
    .aif ENABLE_HAC eq 1
      .aif ENABLE_HSSI eq 1
		mov.l	#~VCRSYS_PMSR2_COREFUNC_HACHSSI, r0
	  .aelse
		mov.l	#~VCRSYS_PMSR2_COREFUNC_DEFAULT, r0
      .aendi
    .aelsif ENABLE_HSSI eq 1
      .aif ENABLE_SRC eq 1
		mov.l	#~VCRSYS_PMSR2_COREFUNC_HSSISRC, r0
      .aelse
		mov.l	#~VCRSYS_PMSR2_COREFUNC_HSSI, r0
      .aendi
	.aelse
		mov.l	#~VCRSYS_PMSR2_COREFUNC_DEFAULT, r0
    .aendi
		mov.l	r0, @r2
    .aif ENABLE_HAC eq 1
      .aif ENABLE_HSSI eq 1
		mov.l	#VCRSYS_PMSR2_COREFUNC_HACHSSI, r0
      .aelse
		mov.l	#VCRSYS_PMSR2_COREFUNC_DEFAULT, r0
      .aendi
    .aelsif ENABLE_HSSI eq 1
      .aif ENABLE_SRC eq 1
		mov.l	#VCRSYS_PMSR2_COREFUNC_HSSISRC, r0
      .aelse
		mov.l	#VCRSYS_PMSR2_COREFUNC_HSSI, r0
      .aendi
	.aelse
		mov.l	#VCRSYS_PMSR2_COREFUNC_DEFAULT, r0
    .aendi
		mov.l	r0, @r1


		; PMSR3 Setting --------------------------------

		mov.l	#VCRSYS_PMMR, r2

		mov.l	#VCRSYS_PMSR3, r1
		mov.l	#~VCRSYS_PMSR3_COREFUNC_DEFAULT, r0
		mov.l	r0, @r2
		mov.l	#VCRSYS_PMSR3_COREFUNC_DEFAULT, r0
		mov.l	r0, @r1


		; PMSR4 Setting --------------------------------

		mov.l	#VCRSYS_PMMR, r2

		mov.l	#VCRSYS_PMSR4, r1
		mov.l	#~VCRSYS_PMSR4_COREFUNC_DEFAULT, r0
		mov.l	r0, @r2
		mov.l	#VCRSYS_PMSR4_COREFUNC_DEFAULT, r0
		mov.l	r0, @r1


		; PMSRG Setting --------------------------------

		mov.l	#VCRSYS_PMMR, r2

		mov.l	#VCRSYS_PMSRG, r1
		mov.l	#~VCRSYS_PMSRG_DEFAULT, r0
		mov.l	r0, @r2
		mov.l	#VCRSYS_PMSRG_DEFAULT, r0
		mov.l	r0, @r1
    
;-------------------------------------------------------
;
; GPIO Initialize

		; All Port is General I/O

		mov.l	#h'00000000, r0
		mov.l	#GPIO_GPIO0_IOINTSEL, r1
		mov.l	r0, @r1

		mov.l	#GPIO_GPIO1_IOINTSEL, r1
		mov.l	r0, @r1

		mov.l	#GPIO_GPIO2_IOINTSEL, r1
		mov.l	r0, @r1

		mov.l	#GPIO_GPIO3_IOINTSEL, r1
		mov.l	r0, @r1

		; GPIO0 Setting

		mov.l	#h'00FFFFFF,r0		;GPIO-0-A0..A23=output
		mov.l	#GPIO_GPIO0_INOUTSEL,r1		;GPIO-0-INOUTSEL
		mov.l	r0,@r1

		; GPIO1 Setting ( ExBus or DataBus)

		; GPIO2 Setting
		mov.l	#h'00000000,r0		;GPIO-2-=no output

		mov.l	#GPIO_GPIO2_INOUTSEL,r1		;GPIO-2-INOUTSEL
		mov.l	r0,@r1

		; GPIO3 Setting (A-21,22 Pin multi for TIMER0,1)

		mov.l	#h'20000000,r0		;GPIO-3-29 change to negative logic
		mov.l	#GPIO_GPIO3_POSNEG,r1		;GPIO-3-POSNEG
		mov.l	r0,@r1
	
		mov.l	#h'3F400000,r0		;GPIO-3-29-24,22 = output

		mov.l	#GPIO_GPIO3_INOUTSEL,r1		;GPIO-3-INOUTSEL
		mov.l	r0,@r1

	.aendi	;"ITS_DS7_COREONLY"
		BRA	FirstSettingFinished
		nop	

		.pool

FirstSettingFinished:
		nop
		nop


;-------------------------------------------------------
;
; First step, setup of SH4R CORE register here was moved to the top of initialization.
;


;-----------------------------------------------------
;
; Setup RTC CLKSEL here was moved to the after SR setting.
;


;-------------------------------------------------------
;
; Wait for 300ms for SH7770-1&1.5cut only. 
; (Pck=50MHz, Div=1024, 1Count=20us, 50Count=1ms)
;

    .aif SH7770_REVISION eq SH7770_1STCUT

		mov.l  #TMU_TSTR0, r1
		mov.b  #h'00, r0
		mov.b  r0, @r1			;// All timer stopped

		mov.l  #TMU_TCR0, r1
		mov.w  #TMU_TCR_TPSC_D1024, r0
		mov.w  r0, @r1			;// Interrupt Disable, Div 1024

		mov.l  #TMU_TCOR0, r1
		mov.l  #h'7000, r0
		mov.l  r0, @r1			;// Set Timer Constant 

		mov.l  #TMU_TCNT0, r1
		mov.l  #h'7000, r0
		mov.l  r0, @r1			;// Initialize Timer Counter

		mov.l  #TMU_TSTR0, r1
		mov.b  #h'01, r0
		mov.b  r0, @r1			;// TMU0 start

		mov.w  #TMU_TCR_UNF, r2

	WAIT_LOOP0:					;// Check Under Flow bit

		mov.l  #TMU_TCR0, r1
		mov.w  @r1, r0
		tst    r2, r0
		bt     WAIT_LOOP0

		mov.l #TMU_TSTR0, r1
		mov.b #h'00, r0
		mov.b r0, @r1			;// All timer stopped

    .aendi	;"SH7770_1STCUT"


;--------------------------------------------------------
;
; Change DDR PAD timing condition	by S.Matsui
;           here was moved to the before cache setting.


;-------------------------------------------------------
;
; FRQCR initialize
;

	;The bug of CPG_FRQCR setup is corrected.(2ndcut and more version) 2004/02/05
    .aif SH7770_REVISION ne SH7770_1STCUT