?? startup.src

?? WinCE5.0BSP for Renesas SH7770
?? SRC
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;=====================================================
; Set CPG for 2ndcut and more	by Hirade
;=====================================================
;	.section ddrpad_1, code, align=4
;	.align 4
;	.export	_set_CPG

set_CPG
;=====================================================
;------ Clock Pulse Generator(CPG)
FRQCR		.equ	h'ffc00000
FRQCR_I		.equ	h'10233035
PLLCR		.equ	h'ffc00024
DLLCSR		.equ	h'ffc40010
DLLFQR		.equ	h'ffc40014
MSTPCR		.equ	h'ffc00030
WDTCNT		.equ	h'ffc40000
WDTCNT_R	.equ	h'5a000001
WDTCSR		.equ	h'ffc40004
WDTCSR_R	.equ	h'a50000e0

;------ CPG settings start-----------------------------
;set_CPG

	mov.l	#I_CPG_0, r0		;in future, CPG setting should be selectable?
	mov.l	#ROMOFFSET, r2	; need's wince
    and		r2, r0			; need's wince
	ldc	r0, GBR
;
	; check event code
	mov.l	#EXPEVT_REG, r1
	mov.l	@r1, r0
	mov.l	#h'00000000, r1	; Power on reset event code
	cmp/eq	r0, r1
	bt	set_CPG_1st

	mov.l	#FRQCR, r1
	mov.l	@r1, r0
	mov.l	#FRQCR_I, r1		;initial value:10233035
	cmp/eq	r0, r1
	bf	set_CPG_2nd
;
set_CPG_1st
	mov.l	#FRQCR, r1
	mov.l	@(_FRQCR, GBR), r0
	mov.l	r0, @r1
;
	mov.l	@r1,r0			;dummy read - 2004/02/05
	mov.l	@r1,r0			;dummy read - 2004/02/05
	mov.l	@r1,r0			;dummy read - 2004/02/05
	mov.l	@r1,r0			;dummy read - 2004/02/05
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
;
; (2nd bug)
;  Manual reset to 3D-SHwtIF module, after set FRQCR. 
;
	mov.l	#WDTCNT, r1
	mov.l	#WDTCNT_R, r0
	mov.l	r0, @r1
	mov.l	#WDTCSR, r1
	mov.l	#WDTCSR_R, r0
	mov.l	r0, @r1
;
;	bra	$
;	nop
;
set_CPG_2nd
;
;	mov.l	@(_PLLCR, GBR), r0
;	mov.l	#PLLCR, r1
;	mov.l	r0, @r1

	mov.l	@(_DLLCSR, GBR), r0
	mov.l	#DLLCSR, r1
	mov.l	r0, @r1
;
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop

;	RTS
;	NOP

	BRA	WAIT_200US
	nop	

;-----------------------------------------------------------------------
;	Early debugging special settings
;-----------------------------------------------------------------------
;	.align  4
I_CPG_0
I_CPG
_FRQCR		.equ	$ - I_CPG	;h'ffc00000
		.data.l	h'40233035	; input clock EXTAL = 33.33MHz			; modified 2004/04/08
					;STC		0 1 0 0	(PLL1 = x12)
					;                   (CPU = 400MHz)
					;                   (SHwy = 200MHz)
					;                   (FIO = 100MHz)
					;		- - - - - - - -
					;                   (IO = 50MHz)
					;P1FC		0 1 0 1 (BUS = 50MHz)
					;
;		.data.l	h'40233034	; input clock EXTAL = 33.33MHz
;					;STC		0 1 0 0	(PLL1 = x12)
;					;IFC		0 0 0 0	(CPU = 400MHz)
;					;CFC		0 0 1 0 (SHwy = 200MHz)
;					;BFC		0 0 1 1 (FIO = 100MHz)
;					;		- - - - - - - -
;					;P2FC		0 1 0 1 (IO = 50MHz)
;					;P1FC		0 1 0 0 (BUS = 66.66MHz)
;
;		.data.l	h'40233036	; input clock EXTAL = 33.33MHz
;					;STC		0 1 0 0	(PLL1 = x12)
;					;IFC		0 0 0 0	(CPU = 400MHz)
;					;CFC		0 0 1 0 (SHwy = 200MHz)
;					;BFC		0 0 1 1 (FIO = 100MHz)
;					;		- - - - - - - -
;					;P2FC		0 1 0 1 (IO = 50MHz)
;					;P1FC		0 1 1 0 (BUS = 33.33MHz)
;					;
;		.data.l	h'30230035	; input clock EXTAL = 33.33MHz
;					;STC		0 0 1 1	(PLL1 = x10)
;					;IFC		0 0 0 0	(CPU = 333MHz)
;					;CFC		0 0 1 0 (SHwy = 166MHz)
;					;BFC		0 0 1 1 (FIO = 83MHz)
;					;		- - - - - - - -
;					;P2FC		0 1 0 1 (IO = 41.5MHz)
;					;P1FC		0 1 0 1 (BUS = 41.5MHz)
;					;
;		.data.l	h'10230055	; input clock EXTAL = 33.33MHz
;					;STC		0 0 0 1	(PLL1 = x8)
;					;IFC		0 0 0 0	(CPU = 266MHz)
;					;CFC		0 0 1 0 (SHwy = 133MHz)
;					;BFC		0 0 1 1 (FIO = 66.66MHz)
;					;		- - - - - - - -
;					;P2FC		0 1 0 1 (IO = 33.33MHz)
;					;P1FC		0 1 0 1 (BUS = 33.33MHz)
;					;
_PLLCR		.equ	$ - I_CPG	;h'ffc00024
		.data.l	h'0000c001		; unused at initialize.
;					;PLL2 enable	1
;					;PLL1 enable	1
;					;		-
;					;		-
;					;		- - - - - - - - - -
;					;CKIO enable	0
;					;also s-standby	1
_DLLCSR		.equ	$ - I_CPG	;h'ffc40010
		.data.l	h'00000000
;					;SCIF9=external	0 0
;					;SCIF8=external	0 0
;					;SCIF7=external	0 0
;					;SCIF6=external	0 0
;					;SCIF5=external	0 0
;					;SCIF4=external	0 0
;					;SCIF3=external	0 0
;					;SCIF2=external	0 0
;					;SCIF1=external	0 0
;					;SCIF0=external	0 0
;					;SSI3=external	0 0
;					;SSI2=external	0 0
;					;SSI1=external	0 0
;					;SSI0=external	0 0
;					;SRC=external	0 0
;					;SPDIF=external	0 0
;					;
_DLLFQR		.equ	$ - I_CPG	;h'ffc40014
		.data.l	h'00000000	;DLL is unused
;					;AUDIO		0 - - - - 0 0 1 1 1 1 1 0 1 0 0
;					;SCI		0 - - - - 0 0 1 1 1 1 1 0 1 0 0
;					;
_MSTPCR		.equ	$ - I_CPG	;h'ffc00030
		.data.l	h'00000000	; unused
;					;		- - - - - -
;					;FPU=enable	0
;					;		- -
;					;INTC=enable	0
;					;SHwy-DMAC=ena	0
;					;		-
;					;H-UDI=enable	0
;					;DBG=enable	0
;					;UBC=enable	0
;					;		-
;					;		- - - - - - - - - - - - - - - -
;=====================================================

	.aelse		;"SH7770_1STCUT"

        mov.l   #CPG_FRQCR,r1
	;The bug of the dummy read at the time of a CPG_FRQCR setup is corrected.(1&1.5cut only)
        mov.l	@r1,r0			;dummy read
        mov.l	@r1,r0			;dummy read
        mov.l	@r1,r0			;dummy read
        mov.l	@r1,r0			;dummy read
        mov.l	@r1,r0			;dummy read
        mov.l   #CPG_FRQCR_CLOCK,r0
        mov.l   r0,@r1
        nop
        nop
        nop
        nop
        nop
        nop
        nop

	.aendi		;"SH7770_1STCUT"

WAIT_200US:
;-------------------------------------------------------
;
; Wait for 200us 
; 200us soft wait. ITS-DS7-PLL(CY2309ZC-1H) is stabilized.
;
		MOV.L	#_SWAIT, R0		;COPY start address of 200us soft wait routine
        mov.l	#ROMOFFSET, r1			; need's wince
        and		r1, r0					; need's wince
		mov.l	r0,r1
		add		#H'00000020, R1
		MOV.L	#H'E500E000, R2		;Destination start address is SH4A-LRAM
WAITLOOP_COPY:
		MOV.L	@R0, R3
		MOV.L	R3, @R2
		ADD		#4, R0
		ADD		#4, R2
		CMP/EQ	R0,R1
		BF		WAITLOOP_COPY		;if T=0 then jump WAITLOOP_COPY
		
;--- Initial Stack Pointer
		MOV.L	#LRAM_SP,r15		;Stack Pointer is LRAM
;---------------------------------------------------;
;Function : SH4A_SYNCO
;---------------------------------------------------;
		.DATA.W		H'00AB	;SYNCO
;---------------------------------------------------;
;Function : SH4A_ICBI
;---------------------------------------------------;
		MOV.L	#H'E500E000, R0
		.DATA.W		H'00E3	;ICBI @R0
		JSR		@R0		; Jump LRAM
		NOP

;---------------------------------------------------------
;
; Memory Controller Unit Setting here was moved to the after BSC setting.
;


;-------------------------------------------------------
;
; DEBUG LED
;
;
;    mov.l   #h'53, r2				; 'S'
;    mov.l   #LED_ALPHA, r3
;    mov.b   r2, @r3
;
;    mov.l   #h'54, r2				; 'T'
;    add     #LED_ALPHA_STRIDE, r3
;    mov.b   r2, @r3
;
;    mov.l   #h'41, r2				; 'A'
;    add     #LED_ALPHA_STRIDE, r3
;    mov.b   r2, @r3
;
;    mov.l   #h'52, r2				; 'R'
;    add     #LED_ALPHA_STRIDE, r3
;    mov.b   r2, @r3
;
;    mov.l   #h'54, r2				; 'T'
;    add     #LED_ALPHA_STRIDE, r3
;    mov.b   r2, @r3

;-------------------------------------------------------
;
; BSC initialize
;

;		mov.l	#BSC_CS0CTRL_DEFAULT,r0		;CS0 width=32bit,CS0 I/F=standard
		mov.l	#h'00000000,r0				;Bus width read,CS0 I/F-standard
		mov.l	#BSC_CS0CTRL,r1				;CS0CTRL(BSC in Busbridge)
		mov.l	r0,@r1
	
		mov.l	#BSC_CS1CTRL_DEFAULT,r0		;CS1 width=32bit,CS1 I/F=standard
		mov.l	#BSC_CS1CTRL,r1				;CS1CTRL(BSC in Busbridge)
		mov.l	r0,@r1

		mov.l	#BSC_ECS0CTRL_DEFAULT,r0	;ECS0 Capacity=1MB,ECS0 width=16,ECS0 I/F=standard
		mov.l	#BSC_ECS0CTRL,r1
		mov.l	r0,@r1
	
		mov.l	#BSC_ECS1CTRL_DEFAULT,r0	;ECS1 Capacity=1MB,ECS1 width=16,ECS1 I/F=standard
		mov.l	#BSC_ECS1CTRL,r1			;ECS1CTRL(BSC in Busbridge)
		mov.l	r0,@r1
	
		mov.l	#BSC_ECS2CTRL_DEFAULT,r0	;ECS2 capacity=8MB,ECS2 width=16,ECS2 I/F=standard
		mov.l	#BSC_ECS2CTRL,r1			;ECS2CTRL(BSC in Busbridge)
		mov.l	r0,@r1
	
		;	Set BSC_ECS3,4,5,6,7CTRL if you need.

		;	Set BSC_CS0BTPH, CS0BSTCTL if you need.

		;	Set BSC_EXDMASET0,1,2,3,4 if you need.

		mov.l	#BSC_EXWTSYNC_DEFAULT,r0	; All disable
		mov.l	#BSC_EXWTSYNC,r1		;EXWTSYNC(BSC in Busbridge)
		mov.l	r0,@r1

;		mov.l	#BSC_CSPWCR0_DEFAULT,r0
		mov.l	#h'00000000,r0			;off(initial value)
		mov.l	#BSC_CSPWCR0,r1			;CSPWCR0(BSC in Busbridge)
		mov.l	r0,@r1
	
;		mov.l	#BSC_CSPWCR1_DEFAULT,r0
		mov.l	#h'00000000,r0			;off(initial value)
		mov.l	#BSC_CSPWCR1,r1			;CSPWCR1(BSC in Busbridge)
		mov.l	r0,@r1
	
;		mov.l	#BSC_ECSPWCR0_DEFAULT,r0
		mov.l	#h'00000000,r0				;outer_wait=invalid,exwait[0]=invalid for Ex-area0
		mov.l	#BSC_ECSPWCR0,r1			;ECSPWCR0(BSC in Busbridge)
		mov.l	r0,@r1
	
		mov.l	#BSC_ECSPWCR1_DEFAULT,r0
		mov.l	#BSC_ECSPWCR1,r1		;ECSPWCR1(BSC in Busbridge)
		mov.l	r0,@r1
	
		mov.l	#BSC_ECSPWCR2_DEFAULT,r0
		mov.l	#BSC_ECSPWCR2,r1			;ECSPWCR2(BSC in Busbridge)
		mov.l	r0,@r1
	
		;	Set BSC_ECSPWCR3,4,5,6,7 if you need.
	
		mov.l	#BSC_CS1GDST_DEFAULT,r0		; GD Enable 2Clock
		mov.l	#BSC_CS1GDST,r1			;CS1GDST(BSC in Busbridge)
		mov.l	r0,@r1
	
		mov.l	#BSC_ECS0GDST_DEFAULT,r0	; GD Enable 2Clock
		mov.l	#BSC_ECS0GDST,r1		;ECS0GDST(BSC in Busbridge)
		mov.l	r0,@r1
	
		mov.l	#BSC_ECS1GDST_DEFAULT,r0	; GD Enable 2Clock
		mov.l	#BSC_ECS1GDST,r1		;ECS1GDST(BSC in Busbridge)
		mov.l	r0,@r1
	
		mov.l	#BSC_ECS2GDST_DEFAULT,r0	; GD Enable 2Clock
		mov.l	#BSC_ECS2GDST,r1		;ECS2GDST(BSC in Busbridge)
		mov.l	r0,@r1
	
		;	Set BSC_ECS3,4,5,6,7GDST if you need.
	
		mov.l	#BSC_CSWCR0_DEFAULT,r0
		mov.l	#BSC_CSWCR0,r1			;CSWCR0(BSC in Busbridge)
		mov.l	r0,@r1
	
		mov.l	#BSC_CSWCR1_DEFAULT,r0
		mov.l	#BSC_CSWCR1,r1			;CSWCR1(BSC in Busbridge)
		mov.l	r0,@r1
	
		mov.l	#BSC_ECSWCR0_DEFAULT,r0
		mov.l	#BSC_ECSWCR0,r1			;ECSWCR0(BSC in Busbridge)
		mov.l	r0,@r1
	
		mov.l	#BSC_ECSWCR1_DEFAULT,r0
		mov.l	#BSC_ECSWCR1,r1			;ECSWCR1(BSC in Busbridge)
		mov.l	r0,@r1
	
		mov.l	#BSC_ECSWCR2_DEFAULT,r0
		mov.l	#BSC_ECSWCR2,r1			;ECSWCR2(BSC in Busbridge)
		mov.l	r0,@r1
	
		;	Set BSC_ECSWCR3,4,5,6,7 if you need.
	
		;	Set BSC_EXDMWCR0,1,2,3,4 if you need.
	
		;	Set BSC_EXDMCR0,1,2,3,4 if you need.
	
		mov.l	#BSC_BCINTMR_DEFAULT,r0
		mov.l	#BSC_BCINTMR,r1			;BCINTMR(BSC in Busbridge)
		mov.l	r0,@r1
	

;-------------------------------------------------------
;
; DEBUG LED
;
;
;    mov.l   #h'53, r2				; 'S'
;    mov.l   #LED_ALPHA, r3
;    mov.b   r2, @r3
;
;    mov.l   #h'54, r2				; 'T'
;    add     #LED_ALPHA_STRIDE, r3
;    mov.b   r2, @r3
;
;    mov.l   #h'41, r2				; 'A'
;    add     #LED_ALPHA_STRIDE, r3
;    mov.b   r2, @r3
;
;    mov.l   #h'52, r2				; 'R'
;    add     #LED_ALPHA_STRIDE, r3
;    mov.b   r2, @r3
;
;    mov.l   #h'54, r2				; 'T'
;    add     #LED_ALPHA_STRIDE, r3
;    mov.b   r2, @r3

;-------------------------------------------------------
;
; Clock Control Reg. Setting
;

		mov.l	#h'00000000, r0 ; All Clock Enable
		mov.l	#VCRSYS_CLKCR, r1
		mov.l	r0, @r1

		BRA	SET_DDR_SDRAM
		NOP
		.POOL
		
SET_DDR_SDRAM:
;---------------------------------------------------------
;
; Memory Controller Unit Setting
;

		; 200us soft wait.
		MOV.L	#_SWAIT, R0		;COPY start address of 200us soft wait routine
        mov.l	#ROMOFFSET, r1			; need's wince
        and		r1, r0					; need's wince
		mov.l	r0,r1
		add		#H'00000020, R1
		MOV.L	#H'E500E000, R2		;Destination start address is SH4A-LRAM
DDR_WAIT_COPY:
		MOV.L	@R0, R3
		MOV.L	R3, @R2
		ADD		#4, R0
		ADD		#4, R2
		CMP/EQ	R0,R1
		BF		DDR_WAIT_COPY		;if T=0 then jump DDR_WAIT_COPY
		MOV.L	#LRAM_SP,r15		;Stack Pointer is LRAM
		.DATA.W		H'00AB			;SH4A_SYNCO
		MOV.L	#H'E500E000, R0
		.DATA.W		H'00E3	;ICBI @R0	;SH4A_ICBI
		JSR		@R0		;Jump LRAM ;soft wait 200usec
		NOP


		mov.l   #EMI_MIM_LOW, R1;	;// MIM (Memory Interface Reg.)
		mov.l   #EMI_MIM_SETUP1, R0
		mov.l   R0, @R1				;// No Auto Refresh, DRE Disable,DCE Enable
									;// Little Endian, 64Bit Bus Width

		;change register setting order SRDA->STR	2004.01.21
		mov.l   #EMI_SDRA_LOW, R0;	;// SDRA (SDRAM Low Attribute Reg.)
		mov.l   #EMI_SDRA_SPLIT_13x9, R1
		mov.l   R1, @R0				;// SDRA.SPLIT=0011 (13x9=16Mx16Bit)

		mov.l   #EMI_STR_LOW, R0;	;// STR (SDRAM Timing Reg.)
		mov.l   #EMI_STR_DEFAULT, R1;// MT46V16M16-TG-75Z

		;//tRFC=75nsec, tWR=15nsec, tRRD=15nsec, tRAS=40nsec,
		;//tRC=65nsec, CL=2, tRCD=20nsec, tRP=20nsec

		mov.l   R1, @R0				;// SRP:2, SRCD:2, CL:2, SRC:7, SRAS:4, SRRC:2,
									;// SWR:2, SRFC:8, RW:3, WR:3 (Unit:Cycle)

		mov.l   #EMI_SCR_LOW, R0;	;// SCR (SDRAM Control Reg.)
		;mov.l   #EMI_SCR_NOP, R1
		;mov.l   R1, @R0				;// SCR.SMS=001 (NOP Command)
		mov.l   #EMI_SCR_CKE, R1
		mov.l   R1, @R0				;// SCR.SMS=011 (CKE Enable, DESELECT Command)
		mov.l   #EMI_SCR_PALL, R1
		mov.l   R1, @R0				;// SCR.SMS=010 (PALL Command)

		mov.l   #H'FEC02000, R0;	;// SDMR (SDRAM Mode Reg.)
		mov.l   #H'00000000, R1
		mov.l   R1, @R0				;// SDMR.BA0=High (EMRS)
									;// DLL=Enable, Drive Stlength=Normal

		; F-E-C----------------0----------------2---------------0---------------0---------0
		;	0-MA13-MA12-MA11 MA10-BA1-BA2-MA9 MA8-MA7-MA6-MA5 MA4-MA3-MA2-MA1 MA0-0-0-0
		;	0    0    0    0    0   0   1   0   0   0   0   0   0   0   0   0   0
		;	                      EMRS                                    Dri DLL
	     	
		mov.l   #H'FEC00908, R0;
		mov.l   R1, @R0				;// SDMR MA0,MA5,MA8=High (MRS)
									;// Burst Length=2, Burst Type=Sequential, CL=2, DLL Reset

		; F-E-C----------------0----------------0---------------9---------------0---------8
		;	0-MA13-MA12-MA11 MA10-BA1-BA2-MA9 MA8-MA7-MA6-MA5 MA4-MA3-MA2-MA1 MA0-0-0-0
		;	0    0    0    0    0   0   0   0   1   0   0   1   0   0   0   0   1
		;	       Normal_Op      MRS         DLL-Res CL=2        Seq BL=2
	     	
		mov.l   #EMI_SCR_LOW, R0; 	;// SCR (SDRAM Control Reg.)
		mov.l   #EMI_SCR_PALL, R1
		mov.l   R1, @R0				;// SCR.SMS=010 (PALL Command)

		mov.l   #EMI_SCR_CBR, R1
		mov.l   R1, @R0				;// SCR.SMS=100 (CBR(Auto)Refresh Command)

		;nop							;// Wait 32 cycle of dsck
		;nop
		;nop
		;nop
		;nop
		;nop

		;mov.l   #EMI_SCR_CBR, R1
		mov.l   R1, @R0				;// SCR.SMS=100 (CBR(Auto)Refresh Command)

		mov.l   #H'FEC00108, R0;	;// SDMR (SDRAM Mode Reg.)
		mov.l   #H'00000000, R1
		mov.l   R1, @R0				;// SDMR MA0, MA5=High (MRS)
									;// Burst Length=2, Burst Type=Sequential, CL=2
		;nop

		; F-E-C----------------0----------------0---------------1---------------0---------8
		;	0-MA13-MA12-MA11 MA10-BA1-BA2-MA9 MA8-MA7-MA6-MA5 MA4-MA3-MA2-MA1 MA0-0-0-0
		;	0    0    0    0    0   0   0   0   0   0   0   1   0   0   0   0   1
		;	       Normal_Op      MRS                 CL=2        Seq BL=2

		; adapt for 2nd cut description from here 

		mov.l   #EMI_SCR_LOW, R0	;MCU_SCR_L
		mov.l   #EMI_SCR_NOP, R1	;NOP

		.AREPEAT        (33)
		mov.l   R1, @R0         ;NOP (wait for more than 200cycle@100MHz)
		.AENDR
?? 文件大小 922 K
?? 上傳用戶 reed2453
?? 所屬分類 Windows CE
??? 相關標簽

#Renesas #WinCE #7770 #5.0
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