//
//  Copyright(C) Renesas Technology Corp. 2004-. All rights reserved.
//
//  header file for SHx Ver.0.8.0
//
//  FILE      : shxtimer.h
//  CREATED   : 2004.09.01
//  MODIFIED  : 
//  AUTHOR    : Renesas Technology Corp.
//  HARDWARE  : RENESAS ITS-DS7
//  HISTORY   : 
//              2004.09.01
//              - Created release code.
//                (based on ASPEN for WCE5.0)

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.

Module Name:

   shxtimer.h

Abstract:

   This header file defines all the SHx timer related constants and structures.

Notes:


--*/

#ifndef _SHX_TIMER_H_
#define _SHX_TIMER_H_

#ifdef SH4
#define TMU_COMMON_REG_SIZE     4   // SH4 - common timer register is of size 4
#else
#define TMU_COMMON_REG_SIZE     2   // SH3 - common timer register is of size 2
#endif

#define TMU_TIMER0_OFFSET       (2 * TMU_COMMON_REG_SIZE)

// common registers
typedef struct _TMU_COMREG {
    BYTE        tstr0;                              // TMU012 timer start register
    BYTE        bPad0[0x1000-1];                      // padding
    BYTE        tstr1;                              // TMU345 timer start register
    BYTE        bPad1[0x1000-1];                      // padding
    BYTE        tstr2;                              // TMU678 timer start register
    BYTE        bPad2[0x1000-1];                      // padding
} TMU_COMREG;
typedef volatile TMU_COMREG *PTMU_COMREG;

// per channel register
typedef struct _TMU_CLOCK_REG {
    DWORD       tcor;           // TMU timer constant register
    DWORD       tcnt;           // TMU timer count register
    WORD        tcr;            // TMU timer control register
    WORD        pad;            // padding, unused
} TMU_CLOCK_REG;
typedef volatile TMU_CLOCK_REG *PTMU_CLOCK_REG;


// bits in TSTR register
#define TMU0_ENABLE             1
#define TMU1_ENABLE             2
#define TMU2_ENABLE             4

// value of interest for counter control registers
//#define TMU_TCR_UNF				0x100	            // counter underflowed
//#define TMU_TCR_UNIE            0x20                // underflow interrupt enable
//#define TMU_TCR_D16             0x01                // PERIPHERAL clock / 16

extern PTMU_COMREG pTmuComReg;
extern PTMU_CLOCK_REG pTmuTimer0, pTmuTimer1, pTmuTimer2;


#endif  // _SHX_TIMER_H_