;
;   Copyright(C) Renesas Technology Corp. 1998-2004. All rights reserved.
;
;   header file for SH-4A Ver.1.0.0
;
;   FILE      : sh4a.inc
;   CREATED   : 1999.04.26
;   MODIFIED  : 2004.04.20
;   AUTHOR    : Renesas Technology Corp.
;   HARDWARE  : RENESAS SH-4A
;   HISTORY   : 
;               2003.06.20
;               - Created release code.
;                 (based on RENESAS ITS-DS4 Source Kit Ver.1.2.0 for WCE4.2)
;               2004.03.04
;               - Added EXPEVT register.
;               2004.04.09
;               - Modified change CPUOPM define value.
;               2004.04.20
;               - Modified change CPUOPM define value.
;

;
; CCN.
;

CCN_REGBASE					.equ	h'FF000000	; CCN Register Base Address
CCN_REGSIZE					.equ	h'40

CCN_CCR_OFFSET				.equ	h'001C		; Cache Control Register Offset
CCN_QACR0_OFFSET			.equ	h'0038		; Queue Address Control Register 0
CCN_QACR1_OFFSET			.equ	h'003C		; Queue Address Control Register 1
CCN_RAMCR_OFFSET			.equ	h'0074		; RAM Control Register

CCN_CCR						.equ	(CCN_REGBASE + CCN_CCR_OFFSET)		; Cache Control Register
CCN_QACR0					.equ	(CCN_REGBASE + CCN_QACR0_OFFSET)	; Queue Address Control Register 0
CCN_QACR1					.equ	(CCN_REGBASE + CCN_QACR1_OFFSET)	; Queue Address Control Register 1
CCN_RAMCR					.equ	(CCN_REGBASE + CCN_RAMCR_OFFSET)	; RAM Control Register

; Cache Control Register

CCN_CCR_ICI					.equ	h'00000800	;IC invalidation
CCN_CCR_ICE					.equ	h'00000100	;IC enable
CCN_CCR_OCI					.equ	h'00000008	;OC invalidation
CCN_CCR_CB					.equ	h'00000004	;Copy-back enable 
CCN_CCR_WT					.equ	h'00000002	;Write-through enable
CCN_CCR_OCE					.equ	h'00000001	;OC enable

;
; The SR reg, puts us in priviledged mode, and blocks all interrupts
;

TM_SR						.equ	h'700000f0

; VBR
VBR_DEFAULT					.equ	h'a0000000

; CPUOPM
CPUOPM_REG					.equ	h'ff2f0000
CPUOPM_DEFAULT				.equ	h'000003e0		; for 3rdCut
CPUOPM_OFF					.equ	h'000003e1		; for 2ndCut

; EXPEVT
EXPEVT_REG					.equ	h'ff000024