?? boot.inc
字號(hào):
;
; Copyright(C) Renesas Technology Corp. 1998-2004. All rights reserved.
;
; header file for ITS-DS7 Ver.1.0.0
;
; FILE : boot.inc
; CREATED : 2002.04.25
; MODIFIED : 2004.06.17
; AUTHOR : Renesas Technology Corp.
; HARDWARE : RENESAS ITS-DS7
; HISTORY :
; 2003.06.20
; - Created release code.
; (based on RENESAS ITS-DS4 Source Kit Ver.1.2.0 for WCE4.2)
; 2003.11.21
; - Names of register definition and initial setting for pin multi
; registers are changed.
; 2004.02.06
; - change initial value. BSC_ECSWCR2_DEFAULT W(7,7,15)R(7,7,15) -> W(0,0,6)R(0,0,6)
; - change initial value. VCRSYS_PMSR2_SCIF0_SCIF0_1 -> VCRSYS_PMSR2_SCIF0_SCIF0
; 2004.03.04
; - optimized CSWCR0/CSWCR1/ECSWCR0.(MiniMonitor v.3.8.5)
; 2004.04.12
; - The FRQCR register setting value was corrected.(Ex-Bus = 50MHz)
; 2004.05.19
; - Modified FRQCR define.
; 2004.06.17
; - Modified CPG comment.
;
; Clock Pulse Generator (CPG)
;
;########################## P=50MHz ##########[I:B:P]=[8:1:1]##########
;MD2=0(EXTAL,PLL1=ON,PLL=x12)
;I:S:B:P2:P1=400:200:100:50:50(input 33.33MHz)
.aif SH7770_REVISION eq SH7770_1STCUT
CPG_FRQCR_CLOCK .equ ( CPG_FRQCR_STC_12 |
+ CPG_FRQCR_IFC_1 |
+ CPG_FRQCR_CFC_1 |
+ CPG_FRQCR_BFC_1_4 |
+ CPG_FRQCR_P2FC_1_8 |
+ CPG_FRQCR_P1FC_1_6 )
.aelse
CPG_FRQCR_CLOCK .equ ( CPG_FRQCR_STC_12 |
+ CPG_FRQCR_IFC_1 |
+ CPG_FRQCR_CFC_1 |
+ CPG_FRQCR_RESERVED |
+ CPG_FRQCR_P1FC_1_8 )
.aendi
;########################################################################
; BSC Register
BSC_CS0CTRL_DEFAULT .equ ( BSC_CSxCTRL_CSxSZ_32BIT |
+ BSC_CSxCTRL_CSxIF_STANDARD )
BSC_CS1CTRL_DEFAULT .equ ( BSC_CSxCTRL_CSxSZ_32BIT |
+ BSC_CSxCTRL_CSxIF_STANDARD )
BSC_ECS0CTRL_DEFAULT .equ ( BSC_ECSxCTRL_ECSxCP_1M |
+ BSC_ECSxCTRL_ECSxSZ_16BIT |
+ BSC_ECSxCTRL_ECSxIF_STANDARD )
BSC_ECS1CTRL_DEFAULT .equ ( BSC_ECSxCTRL_ECSxCP_1M |
+ BSC_ECSxCTRL_ECSxSZ_16BIT |
+ BSC_ECSxCTRL_ECSxIF_STANDARD )
BSC_ECS2CTRL_DEFAULT .equ ( BSC_ECSxCTRL_ECSxCP_8M |
+ BSC_ECSxCTRL_ECSxSZ_16BIT |
+ BSC_ECSxCTRL_ECSxIF_STANDARD )
BSC_ECS3CTRL_DEFAULT .equ ( BSC_ECSxCTRL_ECSxCP_64M |
+ BSC_ECSxCTRL_ECSxSZ_32BIT |
+ BSC_ECSxCTRL_ECSxIF_STANDARD )
BSC_ECS4CTRL_DEFAULT .equ ( BSC_ECSxCTRL_ECSxCP_1M |
+ BSC_ECSxCTRL_ECSxSZ_32BIT |
+ BSC_ECSxCTRL_ECSxIF_STANDARD )
BSC_ECS5CTRL_DEFAULT .equ ( BSC_ECSxCTRL_ECSxCP_1M |
+ BSC_ECSxCTRL_ECSxSZ_32BIT |
+ BSC_ECSxCTRL_ECSxIF_STANDARD )
BSC_ECS6CTRL_DEFAULT .equ ( BSC_ECSxCTRL_ECSxCP_1M |
+ BSC_ECSxCTRL_ECSxSZ_32BIT |
+ BSC_ECSxCTRL_ECSxIF_STANDARD )
BSC_ECS7CTRL_DEFAULT .equ ( BSC_ECSxCTRL_ECSxCP_1M |
+ BSC_ECSxCTRL_ECSxSZ_32BIT |
+ BSC_ECSxCTRL_ECSxIF_STANDARD )
BSC_CS0BSTCTL_DEFAULT .equ h'00000000
BSC_CS1BSTCTL_DEFAULT .equ h'00000000
BSC_CS2BSTCTL_DEFAULT .equ h'00000000
BSC_CS3BSTCTL_DEFAULT .equ h'00000000
BSC_CS4BSTCTL_DEFAULT .equ h'00000000
;BSC_CSWCR0_DEFAULT .equ ( BSC_CSWCR_WRSETUP_1 |
;+ BSC_CSWCR_WRHOLD_1 |
;+ BSC_CSWCR_WRPULSE_4 |
;+ BSC_CSWCR_RDSETUP_1 |
;+ BSC_CSWCR_RDHOLD_2 |
;+ BSC_CSWCR_RDPULSE_9 )
; optimized
BSC_CSWCR0_DEFAULT .equ ( BSC_CSWCR_WRSETUP_0 |
+ BSC_CSWCR_WRHOLD_1 |
+ BSC_CSWCR_WRPULSE_6 |
+ BSC_CSWCR_RDSETUP_4 |
+ BSC_CSWCR_RDHOLD_0 |
+ BSC_CSWCR_RDPULSE_11 )
;BSC_CSWCR1_DEFAULT .equ ( BSC_CSWCR_WRSETUP_1 |
;+ BSC_CSWCR_WRHOLD_1 |
;+ BSC_CSWCR_WRPULSE_4 |
;+ BSC_CSWCR_RDSETUP_1 |
;+ BSC_CSWCR_RDHOLD_2 |
;+ BSC_CSWCR_RDPULSE_9 )
; optimized
BSC_CSWCR1_DEFAULT .equ ( BSC_CSWCR_WRSETUP_0 |
+ BSC_CSWCR_WRHOLD_1 |
+ BSC_CSWCR_WRPULSE_6 |
+ BSC_CSWCR_RDSETUP_0 |
+ BSC_CSWCR_RDHOLD_0 |
+ BSC_CSWCR_RDPULSE_11 )
;BSC_ECSWCR0_DEFAULT .equ ( BSC_CSWCR_WRSETUP_7 |
;+ BSC_CSWCR_WRHOLD_7 |
;+ BSC_CSWCR_WRPULSE_15 |
;+ BSC_CSWCR_RDSETUP_7 |
;+ BSC_CSWCR_RDHOLD_7 |
;+ BSC_CSWCR_RDPULSE_15 )
; optimized
BSC_ECSWCR0_DEFAULT .equ ( BSC_CSWCR_WRSETUP_0 |
+ BSC_CSWCR_WRHOLD_0 |
+ BSC_CSWCR_WRPULSE_6 |
+ BSC_CSWCR_RDSETUP_0 |
+ BSC_CSWCR_RDHOLD_0 |
+ BSC_CSWCR_RDPULSE_7 )
BSC_ECSWCR1_DEFAULT .equ ( BSC_CSWCR_WRSETUP_0 |
+ BSC_CSWCR_WRHOLD_2 |
+ BSC_CSWCR_WRPULSE_8 |
+ BSC_CSWCR_RDSETUP_0 |
+ BSC_CSWCR_RDHOLD_2 |
+ BSC_CSWCR_RDPULSE_8 )
BSC_ECSWCR2_DEFAULT .equ ( BSC_CSWCR_WRSETUP_0 |
+ BSC_CSWCR_WRHOLD_0 |
+ BSC_CSWCR_WRPULSE_6 |
+ BSC_CSWCR_RDSETUP_0 |
+ BSC_CSWCR_RDHOLD_0 |
+ BSC_CSWCR_RDPULSE_6 )
BSC_ECSWCR3_DEFAULT .equ ( BSC_CSWCR_WRSETUP_7 |
+ BSC_CSWCR_WRHOLD_7 |
+ BSC_CSWCR_WRPULSE_15 |
+ BSC_CSWCR_RDSETUP_7 |
+ BSC_CSWCR_RDHOLD_7 |
+ BSC_CSWCR_RDPULSE_15 )
BSC_ECSWCR4_DEFAULT .equ ( BSC_CSWCR_WRSETUP_7 |
+ BSC_CSWCR_WRHOLD_7 |
+ BSC_CSWCR_WRPULSE_15 |
+ BSC_CSWCR_RDSETUP_7 |
+ BSC_CSWCR_RDHOLD_7 |
+ BSC_CSWCR_RDPULSE_15 )
BSC_ECSWCR5_DEFAULT .equ ( BSC_CSWCR_WRSETUP_7 |
+ BSC_CSWCR_WRHOLD_7 |
+ BSC_CSWCR_WRPULSE_15 |
+ BSC_CSWCR_RDSETUP_7 |
+ BSC_CSWCR_RDHOLD_7 |
+ BSC_CSWCR_RDPULSE_15 )
BSC_ECSWCR6_DEFAULT .equ ( BSC_CSWCR_WRSETUP_7 |
+ BSC_CSWCR_WRHOLD_7 |
+ BSC_CSWCR_WRPULSE_15 |
+ BSC_CSWCR_RDSETUP_7 |
+ BSC_CSWCR_RDHOLD_7 |
+ BSC_CSWCR_RDPULSE_15 )
BSC_ECSWCR7_DEFAULT .equ ( BSC_CSWCR_WRSETUP_7 |
+ BSC_CSWCR_WRHOLD_7 |
+ BSC_CSWCR_WRPULSE_15 |
+ BSC_CSWCR_RDSETUP_7 |
+ BSC_CSWCR_RDHOLD_7 |
+ BSC_CSWCR_RDPULSE_15 )
BSC_EXDMWCR0_DEFAULT .equ ( BSC_CSWCR_WRSETUP_7 |
+ BSC_CSWCR_WRHOLD_7 |
+ BSC_CSWCR_WRPULSE_15 |
+ BSC_CSWCR_RDSETUP_7 |
+ BSC_CSWCR_RDHOLD_7 |
+ BSC_CSWCR_RDPULSE_15 )
BSC_EXDMWCR1_DEFAULT .equ ( BSC_CSWCR_WRSETUP_7 |
+ BSC_CSWCR_WRHOLD_7 |
+ BSC_CSWCR_WRPULSE_15 |
+ BSC_CSWCR_RDSETUP_7 |
+ BSC_CSWCR_RDHOLD_7 |
+ BSC_CSWCR_RDPULSE_15 )
BSC_EXDMWCR2_DEFAULT .equ ( BSC_CSWCR_WRSETUP_7 |
+ BSC_CSWCR_WRHOLD_7 |
+ BSC_CSWCR_WRPULSE_15 |
+ BSC_CSWCR_RDSETUP_7 |
+ BSC_CSWCR_RDHOLD_7 |
+ BSC_CSWCR_RDPULSE_15 )
BSC_EXDMWCR3_DEFAULT .equ ( BSC_CSWCR_WRSETUP_7 |
+ BSC_CSWCR_WRHOLD_7 |
+ BSC_CSWCR_WRPULSE_15 |
+ BSC_CSWCR_RDSETUP_7 |
+ BSC_CSWCR_RDHOLD_7 |
+ BSC_CSWCR_RDPULSE_15 )
BSC_EXDMWCR4_DEFAULT .equ ( BSC_CSWCR_WRSETUP_7 |
+ BSC_CSWCR_WRHOLD_7 |
+ BSC_CSWCR_WRPULSE_15 |
+ BSC_CSWCR_RDSETUP_7 |
+ BSC_CSWCR_RDHOLD_7 |
+ BSC_CSWCR_RDPULSE_15 )
BSC_CSPWCR0_DEFAULT .equ ( BSC_CSPWCRx_V_ENABLE |
+ BSC_CSPWCRx_RB_READY |
+ BSC_CSPWCRx_WINV_NORMAL |
+ BSC_CSPWCRx_EXWT2_DISABLE |
+ BSC_CSPWCRx_EXWT1_DISABLE |
+ BSC_CSPWCRx_EXWT0_ENABLE )
BSC_CSPWCR1_DEFAULT .equ ( BSC_CSPWCRx_V_ENABLE |
+ BSC_CSPWCRx_RB_READY |
+ BSC_CSPWCRx_WINV_NORMAL |
+ BSC_CSPWCRx_EXWT2_DISABLE |
+ BSC_CSPWCRx_EXWT1_ENABLE |
+ BSC_CSPWCRx_EXWT0_DISABLE )
BSC_ECSPWCR0_DEFAULT .equ ( BSC_ECSPWCRx_V_ENABLE |
+ BSC_ECSPWCRx_RB_READY |
+ BSC_ECSPWCRx_WINV_NORMAL |
+ BSC_ECSPWCRx_EXWT2_DISABLE |
+ BSC_ECSPWCRx_EXWT1_DISABLE |
+ BSC_ECSPWCRx_EXWT0_ENABLE )
BSC_ECSPWCR1_DEFAULT .equ ( BSC_ECSPWCRx_V_ENABLE |
+ BSC_ECSPWCRx_RB_BUSY |
+ BSC_ECSPWCRx_WINV_INV |
+ BSC_ECSPWCRx_EXWT2_DISABLE |
+ BSC_ECSPWCRx_EXWT1_DISABLE |
+ BSC_ECSPWCRx_EXWT0_ENABLE )
BSC_ECSPWCR2_DEFAULT .equ ( BSC_ECSPWCRx_V_ENABLE |
+ BSC_ECSPWCRx_RB_BUSY |
+ BSC_ECSPWCRx_WINV_INV |
+ BSC_ECSPWCRx_EXWT2_DISABLE |
+ BSC_ECSPWCRx_EXWT1_DISABLE |
+ BSC_ECSPWCRx_EXWT0_ENABLE )
BSC_ECSPWCR3_DEFAULT .equ ( BSC_ECSPWCRx_V_ENABLE |
+ BSC_ECSPWCRx_RB_BUSY |
+ BSC_ECSPWCRx_WINV_INV |
+ BSC_ECSPWCRx_EXWT2_DISABLE |
+ BSC_ECSPWCRx_EXWT1_DISABLE |
+ BSC_ECSPWCRx_EXWT0_ENABLE )
BSC_ECSPWCR4_DEFAULT .equ ( BSC_ECSPWCRx_V_ENABLE |
+ BSC_ECSPWCRx_RB_BUSY |
+ BSC_ECSPWCRx_WINV_INV |
+ BSC_ECSPWCRx_EXWT2_DISABLE |
+ BSC_ECSPWCRx_EXWT1_DISABLE |
+ BSC_ECSPWCRx_EXWT0_ENABLE )
BSC_ECSPWCR5_DEFAULT .equ ( BSC_ECSPWCRx_V_ENABLE |
+ BSC_ECSPWCRx_RB_BUSY |
+ BSC_ECSPWCRx_WINV_INV |
+ BSC_ECSPWCRx_EXWT2_DISABLE |
+ BSC_ECSPWCRx_EXWT1_DISABLE |
+ BSC_ECSPWCRx_EXWT0_ENABLE )
BSC_ECSPWCR6_DEFAULT .equ ( BSC_ECSPWCRx_V_ENABLE |
+ BSC_ECSPWCRx_RB_BUSY |
+ BSC_ECSPWCRx_WINV_INV |
+ BSC_ECSPWCRx_EXWT2_DISABLE |
+ BSC_ECSPWCRx_EXWT1_DISABLE |
+ BSC_ECSPWCRx_EXWT0_ENABLE )
BSC_ECSPWCR7_DEFAULT .equ ( BSC_ECSPWCRx_V_ENABLE |
+ BSC_ECSPWCRx_RB_BUSY |
+ BSC_ECSPWCRx_WINV_INV |
+ BSC_ECSPWCRx_EXWT2_DISABLE |
+ BSC_ECSPWCRx_EXWT1_DISABLE |
+ BSC_ECSPWCRx_EXWT0_ENABLE )
BSC_EXWTSYNC_DEFAULT .equ ( BSC_EXWTSYNC_SYNC2_DISABLE |
+ BSC_EXWTSYNC_SYNC1_DISABLE |
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