+								  BSC_EXWTSYNC_SYNC0_DISABLE	)

;BSC_CS0BSTCTL_DEFAULT	.equ	  BSC_CS0BSTCTL_A0BST_NONE

BSC_CS0BTPH_DEFAULT		.equ	( BSC_CS0BTPH_A0H_0CYCLE		|
+								  BSC_CS0BTPH_A0W_2CYCLE		|
+								  BSC_CS0BTPH_A0B_1CYCLE		)

BSC_CS1GDST_DEFAULT		.equ	( BSC_CS1GDST_CS1GD_ENABLE		|
+								  BSC_CS1GDST_TIMER_SET_2CLOCK	)

BSC_ECS0GDST_DEFAULT	.equ	( BSC_ECSxGDST_CSxGD_ENABLE		|
+								  BSC_ECSxGDST_TIMER_SET_2CLOCK)

BSC_ECS1GDST_DEFAULT	.equ	( BSC_ECSxGDST_CSxGD_ENABLE		|
+								  BSC_ECSxGDST_TIMER_SET_2CLOCK)

BSC_ECS2GDST_DEFAULT	.equ	( BSC_ECSxGDST_CSxGD_ENABLE		|
+								  BSC_ECSxGDST_TIMER_SET_2CLOCK)

BSC_ECS3GDST_DEFAULT	.equ	( BSC_ECSxGDST_CSxGD_ENABLE		|
+								  BSC_ECSxGDST_TIMER_SET_2CLOCK)

BSC_ECS4GDST_DEFAULT	.equ	( BSC_ECSxGDST_CSxGD_ENABLE		|
+								  BSC_ECSxGDST_TIMER_SET_2CLOCK)

BSC_ECS5GDST_DEFAULT	.equ	( BSC_ECSxGDST_CSxGD_ENABLE		|
+								  BSC_ECSxGDST_TIMER_SET_2CLOCK)

BSC_ECS6GDST_DEFAULT	.equ	( BSC_ECSxGDST_CSxGD_ENABLE		|
+								  BSC_ECSxGDST_TIMER_SET_2CLOCK)

BSC_ECS7GDST_DEFAULT	.equ	( BSC_ECSxGDST_CSxGD_ENABLE		|
+								  BSC_ECSxGDST_TIMER_SET_2CLOCK)

BSC_EXDMASET0_DEFAULT	.equ	( BSC_EXDMASETy_DMyECS7_DISABLE	|
+								  BSC_EXDMASETy_DMyECS6_DISABLE	|
+								  BSC_EXDMASETy_DMyECS5_DISABLE	|
+								  BSC_EXDMASETy_DMyECS4_DISABLE	|
+								  BSC_EXDMASETy_DMyECS3_DISABLE	|
+								  BSC_EXDMASETy_DMyECS2_DISABLE	|
+								  BSC_EXDMASETy_DMyECS1_DISABLE	|
+								  BSC_EXDMASETy_DMyECS0_DISABLE	|
+								  BSC_EXDMASETy_DMyCS1_DISABLE	)

BSC_EXDMASET1_DEFAULT	.equ	( BSC_EXDMASETy_DMyECS7_DISABLE	|
+								  BSC_EXDMASETy_DMyECS6_DISABLE	|
+								  BSC_EXDMASETy_DMyECS5_DISABLE	|
+								  BSC_EXDMASETy_DMyECS4_DISABLE	|
+								  BSC_EXDMASETy_DMyECS3_DISABLE	|
+								  BSC_EXDMASETy_DMyECS2_DISABLE	|
+								  BSC_EXDMASETy_DMyECS1_DISABLE	|
+								  BSC_EXDMASETy_DMyECS0_DISABLE	|
+								  BSC_EXDMASETy_DMyCS1_DISABLE	)

BSC_EXDMASET2_DEFAULT	.equ	( BSC_EXDMASETy_DMyECS7_DISABLE	|
+								  BSC_EXDMASETy_DMyECS6_DISABLE	|
+								  BSC_EXDMASETy_DMyECS5_DISABLE	|
+								  BSC_EXDMASETy_DMyECS4_DISABLE	|
+								  BSC_EXDMASETy_DMyECS3_DISABLE	|
+								  BSC_EXDMASETy_DMyECS2_DISABLE	|
+								  BSC_EXDMASETy_DMyECS1_DISABLE	|
+								  BSC_EXDMASETy_DMyECS0_DISABLE	|
+								  BSC_EXDMASETy_DMyCS1_DISABLE	)

BSC_EXDMASET3_DEFAULT	.equ	( BSC_EXDMASETy_DMyECS7_DISABLE	|
+								  BSC_EXDMASETy_DMyECS6_DISABLE	|
+								  BSC_EXDMASETy_DMyECS5_DISABLE	|
+								  BSC_EXDMASETy_DMyECS4_DISABLE	|
+								  BSC_EXDMASETy_DMyECS3_DISABLE	|
+								  BSC_EXDMASETy_DMyECS2_DISABLE	|
+								  BSC_EXDMASETy_DMyECS1_DISABLE	|
+								  BSC_EXDMASETy_DMyECS0_DISABLE	|
+								  BSC_EXDMASETy_DMyCS1_DISABLE	)

BSC_EXDMASET4_DEFAULT	.equ	( BSC_EXDMASETy_DMyECS7_DISABLE	|
+								  BSC_EXDMASETy_DMyECS6_DISABLE	|
+								  BSC_EXDMASETy_DMyECS5_DISABLE	|
+								  BSC_EXDMASETy_DMyECS4_DISABLE	|
+								  BSC_EXDMASETy_DMyECS3_DISABLE	|
+								  BSC_EXDMASETy_DMyECS2_DISABLE	|
+								  BSC_EXDMASETy_DMyECS1_DISABLE	|
+								  BSC_EXDMASETy_DMyECS0_DISABLE	|
+								  BSC_EXDMASETy_DMyCS1_DISABLE	)

BSC_EXDMCR0_DEFAULT		.equ	( BSC_EXDMCRy_EXDY_DISABLE	|
+								  BSC_EXDMCRy_EXDS_LEVEL	|
+								  BSC_EXDMCRy_EXRS_1CLOCK	|
+								  BSC_EXDMCRy_EXRL_HIGH		|
+								  BSC_EXDMCRy_EXAL_HIGH		|
+								  BSC_EXDMCRy_EXAC_BOTH	)

BSC_EXDMCR1_DEFAULT		.equ	( BSC_EXDMCRy_EXDY_DISABLE	|
+								  BSC_EXDMCRy_EXDS_LEVEL	|
+								  BSC_EXDMCRy_EXRS_1CLOCK	|
+								  BSC_EXDMCRy_EXRL_HIGH		|
+								  BSC_EXDMCRy_EXAL_HIGH		|
+								  BSC_EXDMCRy_EXAC_BOTH	)

BSC_EXDMCR2_DEFAULT		.equ	( BSC_EXDMCRy_EXDY_DISABLE	|
+								  BSC_EXDMCRy_EXDS_LEVEL	|
+								  BSC_EXDMCRy_EXRS_1CLOCK	|
+								  BSC_EXDMCRy_EXRL_HIGH		|
+								  BSC_EXDMCRy_EXAL_HIGH		|
+								  BSC_EXDMCRy_EXAC_BOTH	)

BSC_EXDMCR3_DEFAULT		.equ	( BSC_EXDMCRy_EXDY_DISABLE	|
+								  BSC_EXDMCRy_EXDS_LEVEL	|
+								  BSC_EXDMCRy_EXRS_1CLOCK	|
+								  BSC_EXDMCRy_EXRL_HIGH		|
+								  BSC_EXDMCRy_EXAL_HIGH		|
+								  BSC_EXDMCRy_EXAC_BOTH	)

BSC_EXDMCR4_DEFAULT		.equ	( BSC_EXDMCRy_EXDY_DISABLE	|
+								  BSC_EXDMCRy_EXDS_LEVEL	|
+								  BSC_EXDMCRy_EXRS_1CLOCK	|
+								  BSC_EXDMCRy_EXRL_HIGH		|
+								  BSC_EXDMCRy_EXAL_HIGH		|
+								  BSC_EXDMCRy_EXAC_BOTH		)

BSC_BCINTMR_DEFAULT		.equ	( BSC_BCINTMR_ATTEM_DISABLE )

; Pin Multi Register

VCRSYS_PMSR1_COREONLY_DEFAULT	.equ	( VCRSYS_PMSR1_IR5_EX_CS7	|
+								  VCRSYS_PMSR1_IR4_EX_CS6	|
+								  VCRSYS_PMSR1_IR3_EX_CS5	|
+								  VCRSYS_PMSR1_IR2_EX_WAIT2	|
+								  VCRSYS_PMSR1_IR1_EX_WAIT1	|
+								  VCRSYS_PMSR1_EXA_EXBUS	|
+								  VCRSYS_PMSR1_ATAPI_ATAPI	|
+								  VCRSYS_PMSR1_EXD31_EXBUS	|
+								  VCRSYS_PMSR1_EXD15_EXBUS	|
+								  VCRSYS_PMSR1_EXCP_EXCS	|
+								  VCRSYS_PMSR1_EXCS1_EXCS	|
+								  VCRSYS_PMSR1_EXCS0_EXCS	|
+								  VCRSYS_PMSR1_CS1_CS		|
+								  VCRSYS_PMSR1_DREQ1_DREQ	|
+								  VCRSYS_PMSR1_DREQ0_DREQ	|
+								  VCRSYS_PMSR1_DACK1_DACK	|
+								  VCRSYS_PMSR1_DACK0_DACK	|
+								  VCRSYS_PMSR1_DRACK0_DRACK	)

VCRSYS_PMSR1_COREFUNC_DEFAULT	.equ	( VCRSYS_PMSR1_IR5_EX_CS7	|
+								  VCRSYS_PMSR1_IR4_EX_CS6	|
+								  VCRSYS_PMSR1_IR3_EX_CS5	|
+								  VCRSYS_PMSR1_IR2_EX_WAIT2	|
+								  VCRSYS_PMSR1_IR1_EX_WAIT1	|
+								  VCRSYS_PMSR1_EXA_EXBUS	|
+								  VCRSYS_PMSR1_ATAPI_ATAPI	|
+								  VCRSYS_PMSR1_EXD31_EXBUS	|
+								  VCRSYS_PMSR1_EXD15_EXBUS	|
+								  VCRSYS_PMSR1_EXCP_EXCS	|
+								  VCRSYS_PMSR1_EXCS1_EXCS	|
+								  VCRSYS_PMSR1_EXCS0_EXCS	|
+								  VCRSYS_PMSR1_CS1_CS		|
+								  VCRSYS_PMSR1_DREQ1_DREQ	|
+								  VCRSYS_PMSR1_DREQ0_DREQ	|
+								  VCRSYS_PMSR1_DACK1_DACK	|
+								  VCRSYS_PMSR1_DACK0_DACK	|
+								  VCRSYS_PMSR1_DRACK0_DRACK	)

VCRSYS_PMSR2_COREONLY_DEFAULT	.equ	( VCRSYS_PMSR2_SCICK_SCIF	|
+								  VCRSYS_PMSR2_SCIF9_GPIO	|
+								  VCRSYS_PMSR2_SCIF7_SCIF	|
+								  VCRSYS_PMSR2_SCIF6_I2C	|
+								  VCRSYS_PMSR2_SCIF4_SCIF	|
+								  VCRSYS_PMSR2_SCIF3_GPIO	|
+								  VCRSYS_PMSR2_SCIF2_SCIF	|
+								  VCRSYS_PMSR2_SCIF0_SCIF0	|
+								  VCRSYS_PMSR2_ADOCK_AUDIO	|
+								  VCRSYS_PMSR2_HARES_SSI	|
+								  VCRSYS_PMSR2_SSI23_SSI	|
+								  VCRSYS_PMSR2_SSI1_SSI		|
+								  VCRSYS_PMSR2_SSI0_SSI		|
+								  VCRSYS_PMSR2_SPDIF1_GPIO	|
+								  VCRSYS_PMSR2_SPDIF0_GPIO	|
+								  VCRSYS_PMSR2_CDE_CDE		|
+								  VCRSYS_PMSR2_ODDF_GPIO	)

VCRSYS_PMSR2_COREFUNC_DEFAULT	.equ	( VCRSYS_PMSR2_SCICK_SCIF	|
+								  VCRSYS_PMSR2_SCIF9_SCIF	|
+								  VCRSYS_PMSR2_SCIF7_SCIF	|
+								  VCRSYS_PMSR2_SCIF6_I2C	|
+								  VCRSYS_PMSR2_SCIF4_SCIF	|
+								  VCRSYS_PMSR2_SCIF3_SCIF	|
+								  VCRSYS_PMSR2_SCIF2_SCIF	|
+								  VCRSYS_PMSR2_SCIF0_SCIF0	|
+								  VCRSYS_PMSR2_ADOCK_AUDIO	|
+								  VCRSYS_PMSR2_HARES_HAC	|
+								  VCRSYS_PMSR2_SSI23_HAC	|
+								  VCRSYS_PMSR2_SSI1_GPIO	|
+								  VCRSYS_PMSR2_SSI0_SSI	|
+								  VCRSYS_PMSR2_SPDIF1_SPDIF	|
+								  VCRSYS_PMSR2_SPDIF0_SPDIF	|
+								  VCRSYS_PMSR2_CDE_CDE		|
+								  VCRSYS_PMSR2_ODDF_ODDF	)

VCRSYS_PMSR2_COREFUNC_HACHSSI	.equ	( VCRSYS_PMSR2_SCICK_SCIF	|
+								  VCRSYS_PMSR2_SCIF9_SCIF	|
+								  VCRSYS_PMSR2_SCIF7_SCIF	|
+								  VCRSYS_PMSR2_SCIF6_I2C	|
+								  VCRSYS_PMSR2_SCIF4_SCIF	|
+								  VCRSYS_PMSR2_SCIF3_SCIF	|
+								  VCRSYS_PMSR2_SCIF2_SCIF	|
+								  VCRSYS_PMSR2_SCIF0_SCIF0	|
+								  VCRSYS_PMSR2_ADOCK_AUDIO	|
+								  VCRSYS_PMSR2_HARES_HAC	|
+								  VCRSYS_PMSR2_SSI23_HAC	|
+								  VCRSYS_PMSR2_SSI1_GPIO	|
+								  VCRSYS_PMSR2_SSI0_SSI	|
+								  VCRSYS_PMSR2_SPDIF1_SPDIF	|
+								  VCRSYS_PMSR2_SPDIF0_SPDIF	|
+								  VCRSYS_PMSR2_CDE_CDE		|
+								  VCRSYS_PMSR2_ODDF_ODDF	)

VCRSYS_PMSR2_COREFUNC_HSSI	.equ	( VCRSYS_PMSR2_SCICK_SCIF	|
+								  VCRSYS_PMSR2_SCIF9_SCIF	|
+								  VCRSYS_PMSR2_SCIF7_SCIF	|
+								  VCRSYS_PMSR2_SCIF6_I2C	|
+								  VCRSYS_PMSR2_SCIF4_SCIF	|
+								  VCRSYS_PMSR2_SCIF3_SCIF	|
+								  VCRSYS_PMSR2_SCIF2_SCIF	|
+								  VCRSYS_PMSR2_SCIF0_SCIF0	|
+								  VCRSYS_PMSR2_ADOCK_AUDIO	|
+								  VCRSYS_PMSR2_HARES_SSI	|
+								  VCRSYS_PMSR2_SSI23_SSI	|
+								  VCRSYS_PMSR2_SSI1_SSI		|
+								  VCRSYS_PMSR2_SSI0_SSI		|
+								  VCRSYS_PMSR2_SPDIF1_SPDIF	|
+								  VCRSYS_PMSR2_SPDIF0_SPDIF	|
+								  VCRSYS_PMSR2_CDE_CDE		|
+								  VCRSYS_PMSR2_ODDF_ODDF	)

VCRSYS_PMSR2_COREFUNC_HSSISRC	.equ	( VCRSYS_PMSR2_SCICK_SCIF	|
+								  VCRSYS_PMSR2_SCIF9_SCIF	|
+								  VCRSYS_PMSR2_SCIF7_SCIF	|
+								  VCRSYS_PMSR2_SCIF6_I2C	|
+								  VCRSYS_PMSR2_SCIF4_SCIF	|
+								  VCRSYS_PMSR2_SCIF3_SCIF	|
+								  VCRSYS_PMSR2_SCIF2_SCIF	|
+								  VCRSYS_PMSR2_SCIF0_SCIF0	|
+								  VCRSYS_PMSR2_ADOCK_AUDIO	|
+								  VCRSYS_PMSR2_HARES_SSI	|
+								  VCRSYS_PMSR2_SSI23_SSI	|
+								  VCRSYS_PMSR2_SSI1_SSI		|
+								  VCRSYS_PMSR2_SSI0_SSI		|
+								  VCRSYS_PMSR2_SPDIF1_SPDIF	|
+								  VCRSYS_PMSR2_SPDIF0_SPDIF	|
+								  VCRSYS_PMSR2_CDE_CDE		|
+								  VCRSYS_PMSR2_ODDF_ODDF	)

VCRSYS_PMSR3_COREONLY_DEFAULT	.equ	( VCRSYS_PMSR3_REMC_GPIO	|
+								  VCRSYS_PMSR3_TIME1_GPIO	|
+								  VCRSYS_PMSR3_TIME0_GPIO	|
+								  VCRSYS_PMSR3_CANB_GPIO	|
+								  VCRSYS_PMSR3_CANA_GPIO	)

VCRSYS_PMSR3_COREFUNC_DEFAULT	.equ	( VCRSYS_PMSR3_REMC_IRREC	|
+								  VCRSYS_PMSR3_TIME1_GPIO	|
+								  VCRSYS_PMSR3_TIME0_PWM	|
+								  VCRSYS_PMSR3_CANB_GPIO	|
+								  VCRSYS_PMSR3_CANA_GPIO	)

VCRSYS_PMSR4_COREONLY_DEFAULT	.equ	( VCRSYS_PMSR4_VID_GPIO		|
+								  VCRSYS_PMSR4_DAK2_DACK	|
+								  VCRSYS_PMSR4_AUD_GPIO		|
+								  VCRSYS_PMSR4_DISP_DISP	|
+								  VCRSYS_PMSR4_DCKO_DOTCLK	|
+								  VCRSYS_PMSR4_SDBUP_SDBUP	|
+								  VCRSYS_PMSR4_SDSELF_SDSELF	|
+								  VCRSYS_PMSR4_RESOUT_RESOUT)

VCRSYS_PMSR4_COREFUNC_DEFAULT	.equ	( VCRSYS_PMSR4_VID_VIDEOIN		|
+								  VCRSYS_PMSR4_DAK2_DACK	|
+								  VCRSYS_PMSR4_AUD_GPIO		|
+								  VCRSYS_PMSR4_DISP_DISP	|
+								  VCRSYS_PMSR4_DCKO_DOTCLK	|
+								  VCRSYS_PMSR4_SDBUP_SDBUP	|
+								  VCRSYS_PMSR4_SDSELF_SDSELF	|
+								  VCRSYS_PMSR4_RESOUT_RESOUT)

VCRSYS_PMSRG_DEFAULT	.equ	( VCRSYS_PMSRG_A25_EXBUS	|
+								  VCRSYS_PMSRG_A24_EXBUS	|
+								  VCRSYS_PMSRG_A23_EXBUS	|
+								  VCRSYS_PMSRG_A22_EXBUS	|
+								  VCRSYS_PMSRG_A21_EXBUS	|
+								  VCRSYS_PMSRG_A20_EXBUS	|
+								  VCRSYS_PMSRG_A19_EXBUS	|
+								  VCRSYS_PMSRG_A18_EXBUS	|
+								  VCRSYS_PMSRG_A17_EXBUS	|
+								  VCRSYS_PMSRG_A16_EXBUS	|
+								  VCRSYS_PMSRG_A15_EXBUS	|
+								  VCRSYS_PMSRG_A14_EXBUS	|
+								  VCRSYS_PMSRG_A13_EXBUS	|
+								  VCRSYS_PMSRG_A12_EXBUS	|
+								  VCRSYS_PMSRG_A11_EXBUS	)


; Cache Control Register

CCN_CCR_FLUSH					.equ	CCN_CCR_ICI | CCN_CCR_OCI
CCN_CCR_ENABLE					.equ	CCN_CCR_ICE | CCN_CCR_OCE | CCN_CCR_CB
CCN_CCR_DISABLE					.equ	0