//
//  Copyright(C) Renesas Technology Corp. 2003-2004. All rights reserved.
//
//  header file for ITS-DS7 Ver.1.0.0
//
//  FILE      : SH7770.h
//  CREATED   : 2003.06.20
//  MODIFIED  : 2004.12.28
//  AUTHOR    : Renesas Technology Corp.
//  HARDWARE  : RENESAS ITS-DS7
//  HISTORY   : 
//              2003.06.20
//              - Created release code.
//              2003.11.21
//              - Register definition for bus bridge is added.
//              2004.03.04
//              - Deleted SH7770_2NDCUT.
//              2004.03.10
//              - Modified TMU345,TMU678 register offset.
//              2004.04.09
//              - Modified Revival 2NDCUT for setting of CPUOPM.
//              2004.04.12
//              - Modified FRQCR register setting value was corrected.(Ex-Bus = 50MHz)
//              2004.05.19
//              - Modified FRQCR define.
//              2004.09.01
//              - Created release code for WCE5.0.
//              2004.12.28
//              - Modified INTC_USERIMASK.

#ifndef _SH7770_H_
#define _SH7770_H_

// define for CHIP_REVISION

#define SH7770_1STCUT			1
#define SH7770_2NDCUT			2
#define SH7770_FINALCUT			99

//
// SH7770 Chip module offsets (AREA7)
//

#define DUMMY_OFFSET           0x00000000

#define	SH7770_DEBUG_OFFSET		0x00000000
#define	SH7770_DEBUG_BASE		(AREA_7+DUMMY_OFFSET + SH7770_DEBUG_OFFSET)
#define	SH7770_MBX_OFFSET		0x01000000
#define	SH7770_MBX_BASE		(AREA_7+DUMMY_OFFSET + SH7770_MBX_OFFSET)
#define	SH7770_SHWYDMAC_OFFSET	0x02000000
#define	SH7770_SHWYDMAC_BASE		(AREA_7+DUMMY_OFFSET + SH7770_SHWYDMAC_OFFSET)
#define	SH7770_EMI_OFFSET		0x02800000
#define	SH7770_EMI_BASE		(AREA_7+DUMMY_OFFSET + SH7770_EMI_OFFSET)
#define	SH7770_COREERR_OFFSET		0x03000000
#define	SH7770_COREERR_BASE		(AREA_7+DUMMY_OFFSET + SH7770_COREERR_OFFSET)
#define	SH7770_COREUBC_OFFSET		0x03200000
#define	SH7770_COREUBC_BASE		(AREA_7+DUMMY_OFFSET + SH7770_COREUBC_OFFSET)
#define	SH7770_SHWYROUTER_OFFSET	0x03400000
#define	SH7770_SHWYROUTER_BASE	(AREA_7+DUMMY_OFFSET + SH7770_SHWYROUTER_OFFSET)
#define	SH7770_BUSBRIDGE_OFFSET	0x03800000
#define	SH7770_BUSBRIDGE_BASE		(AREA_7+DUMMY_OFFSET + SH7770_BUSBRIDGE_OFFSET)

//
// for Bus bridge Internal Register
//
#define	SH7770_VCRSYS_OFFSET		0x00000000
#define	SH7770_BSC_OFFSET		0x00000200
#define	SH7770_DMAC_OFFSET		0x00001000

//
// for Bus bridge Internal IP
//
#define	SH7770_YUV_OFFSET		    0x00100000
#define	SH7770_VIN_OFFSET		    0x00101000
#define	SH7770_ATAPI_OFFSET		    0x00102000
#define	SH7770_USBHOST_OFFSET		    0x00103000
#define	SH7770_USBFUNC_OFFSET		    0x00104000
#define	SH7770_SPDIF_OFFSET		    0x00105000
#define	SH7770_HAC_OFFSET		    0x00106000
#define	SH7770_I2C_OFFSET		    0x00107000
#define	SH7770_HCAN_OFFSET		    0x00108000
#define	SH7770_SSI0_OFFSET		    0x00110000
#define	SH7770_SSI1_OFFSET		    0x00111000
#define	SH7770_SSI2_OFFSET		    0x00112000
#define	SH7770_SSI3_OFFSET		    0x00113000
#define	SH7770_SRC_OFFSET		    0x00122000
#define	SH7770_SCIF0_OFFSET		    0x00123000
#define	SH7770_SCIF1_OFFSET		    0x00124000
#define	SH7770_SCIF2_OFFSET             0x00125000
#define	SH7770_SCIF3_OFFSET             0x00126000
#define	SH7770_SCIF4_OFFSET             0x00127000
#define	SH7770_SCIF5_OFFSET             0x00128000
#define	SH7770_SCIF6_OFFSET             0x00129000
#define	SH7770_SCIF7_OFFSET             0x0012A000
#define	SH7770_SCIF8_OFFSET             0x0012B000
#define	SH7770_SCIF9_OFFSET             0x0012C000
#define	SH7770_HSPI0_OFFSET             0x0012F000
#define	SH7770_HSPI1_OFFSET             0x00130000
#define	SH7770_PWM_OFFSET               0x00131000
#define	SH7770_REMOCON_OFFSET           0x00137000
#define	SH7770_MOST_OFFSET              0x0013A000
#define	SH7770_ADC_OFFSET               0x0013C000
#define	SH7770_GPS_OFFSET               0x0013D000
#define	SH7770_GPIO_OFFSET              0x0013E000
#define	SH7770_INTC_USERIMASK_OFFSET    0x00150000
#define	SH7770_CPG_OFFSET               0x00400000
#define	SH7770_RESET_OFFSET             0x00440000
#define	SH7770_RTC_OFFSET               0x00480000
#define	SH7770_INTC_OFFSET              0x00500000
#define	SH7770_TMU012_OFFSET            0x00580000
#define	SH7770_TMU345_OFFSET            0x00581000
#define	SH7770_TMU678_OFFSET            0x00582000
#define	SH7770_INTC2_OFFSET             0x00600000
#define	SH7770_2DG_OFFSET               0x00680000
#define	SH7770_DU_OFFSET                0x00700000

//
// for Bus bridge
//     Definitions for VCRSYS
//
#define	VCRSYS_REGBASE			(SH7770_BUSBRIDGE_BASE+SH7770_VCRSYS_OFFSET)
#define	VCRSYS_REGSIZE			0x00000200

#define	VCRSYS_BBGVCR0_OFFSET		0x00000000
#define	VCRSYS_BBGVCR1_OFFSET           0x00000004
#define	VCRSYS_BBGVCEAR_OFFSET             0x00000008
#define	VCRSYS_CLKCR_OFFSET             0x0000000C
#define	VCRSYS_PMMR_OFFSET              0x00000010
#define	VCRSYS_PMSR1_OFFSET             0x00000014
#define	VCRSYS_PMSR2_OFFSET             0x00000018
#define	VCRSYS_PMSR3_OFFSET             0x0000001C
#define	VCRSYS_PMSR4_OFFSET             0x00000020
#define	VCRSYS_PMSRG_OFFSET            0x00000024
#define	VCRSYS_DBGSTR_OFFSET            0x00000028
#define	VCRSYS_DBR2_OFFSET            0x00000040
#define	VCRSYS_DRR2_OFFSET            0x00000044
#define	VCRSYS_DAR2_OFFSET            0x00000048
#define	VCRSYS_DAMR2_OFFSET            0x0000004C
#define	VCRSYS_DCBR10_OFFSET            0x00000050
#define	VCRSYS_DBR3_OFFSET            0x00000060
#define	VCRSYS_DRR3_OFFSET            0x00000064
#define	VCRSYS_DAR3_OFFSET            0x00000068
#define	VCRSYS_DAMR3_OFFSET            0x0000006C
#define	VCRSYS_DCBR11_OFFSET            0x00000070
#define	VCRSYS_ECPUCR_OFFSET            0x00000100
#define	VCRSYS_ECPUMR_OFFSET            0x00000104
#define	VCRSYS_BBGIR_OFFSET            0x00000108
#define	VCRSYS_ECPUIR_OFFSET            0x0000010C
#define	VCRSYS_ECPUER_OFFSET            0x00000110
#define	VCRSYS_ECPUEIR_OFFSET            0x00000114


#define	VCRSYS_BBGVCR0			(VCRSYS_REGBASE + VCRSYS_BBGVCR0_OFFSET)
#define	VCRSYS_BBGVCR1			(VCRSYS_REGBASE + VCRSYS_BBGVCR1_OFFSET)
#define	VCRSYS_BBGVCEAR			(VCRSYS_REGBASE + VCRSYS_BBGVCEAR_OFFSET)
#define	VCRSYS_CLKCR			(VCRSYS_REGBASE + VCRSYS_CLKCR_OFFSET)
#define	VCRSYS_PMMR				(VCRSYS_REGBASE + VCRSYS_PMMR_OFFSET)
#define	VCRSYS_PMSR1			(VCRSYS_REGBASE + VCRSYS_PMSR1_OFFSET)
#define	VCRSYS_PMSR2			(VCRSYS_REGBASE + VCRSYS_PMSR2_OFFSET)
#define	VCRSYS_PMSR3			(VCRSYS_REGBASE + VCRSYS_PMSR3_OFFSET)
#define	VCRSYS_PMSR4			(VCRSYS_REGBASE + VCRSYS_PMSR4_OFFSET)
#define	VCRSYS_PMSRG			(VCRSYS_REGBASE + VCRSYS_PMSRG_OFFSET)
#define	VCRSYS_DGBSTR			(VCRSYS_REGBASE + VCRSYS_DBGSTR_OFFSET)
#define	VCRSYS_DBR2				(VCRSYS_REGBASE + VCRSYS_DBR2_OFFSET)
#define	VCRSYS_DRR2				(VCRSYS_REGBASE + VCRSYS_DRR2_OFFSET)
#define	VCRSYS_DAR2				(VCRSYS_REGBASE + VCRSYS_DAR2_OFFSET)
#define	VCRSYS_DAMR2			(VCRSYS_REGBASE + VCRSYS_DAMR2_OFFSET)
#define	VCRSYS_DCBR10			(VCRSYS_REGBASE + VCRSYS_DCBR10_OFFSET)
#define	VCRSYS_DBR3				(VCRSYS_REGBASE + VCRSYS_DBR3_OFFSET)
#define	VCRSYS_DRR3				(VCRSYS_REGBASE + VCRSYS_DRR3_OFFSET)
#define	VCRSYS_DAR3				(VCRSYS_REGBASE + VCRSYS_DAMR3_OFFSET)
#define	VCRSYS_DAMR3			(VCRSYS_REGBASE + VCRSYS_DAMR3_OFFSET)
#define	VCRSYS_DCBR11			(VCRSYS_REGBASE + VCRSYS_DCBR11_OFFSET)
#define	VCRSYS_ECPUCR			(VCRSYS_REGBASE + VCRSYS_ECPUCR_OFFSET)
#define	VCRSYS_ECPUMR			(VCRSYS_REGBASE + VCRSYS_ECPUMR_OFFSET)
#define	VCRSYS_BBGIR			(VCRSYS_REGBASE + VCRSYS_BBGIR_OFFSET)
#define	VCRSYS_ECPUIR			(VCRSYS_REGBASE + VCRSYS_ECPUIR_OFFSET)
#define	VCRSYS_ECPUER			(VCRSYS_REGBASE + VCRSYS_ECPUER_OFFSET)
#define	VCRSYS_ECPUEIR			(VCRSYS_REGBASE + VCRSYS_ECPUEIR_OFFSET)

// Definitions for VCRSYS BBGVCR1
#define	VCRSYS_BBGVCR1_MERR_FLAGS	0x0000FF00	// Display MERR FLAGS
#define	VCRSYS_BBGVCR1_MERR_WT_CNL	0x00000800	// Display MERR FLAGS(WT_CNL)
#define	VCRSYS_BBGVCR1_MERR_BAD_BE	0x00000400	// Display MERR FLAGS(BAD_BE)
#define	VCRSYS_BBGVCR1_MERR_BAD_SIZE	0x00000200	// Display MERR FLAGS(BAD_SIZE)
#define	VCRSYS_BBGVCR1_MERR_BAD_TRS	0x00000100	// Display MERR FLAGS(BAD_TRS)
#define	VCRSYS_BBGVCR1_PERR_FLAGS	0x0000002F	// Display PERR_FLAGS
#define	VCRSYS_BBGVCR1_PERR_BAD_OPC		0x00000020	// Display PERR_FLAGS (Received Not-support opcode)
#define	VCRSYS_BBGVCR1_PERR_UNSOL_RESP	0x00000008	// Display PERR_FLAGS (Received Uncorresponding response packet)
#define	VCRSYS_BBGVCR1_PERR_BAD_ADDR		0x00000004	// Display PERR_FLAGS (Received Undefined Area access)
#define	VCRSYS_BBGVCR1_PERR_ERR_SNT		0x00000002	// Display PERR_FLAGS (Sent Error Response)
#define	VCRSYS_BBGVCR1_PERR_ERR_RCV		0x00000001	// Display PERR_FLAGS (Received Error Response)

// Definitions for VCRSYS CLKCR
#define	VCRSYS_CLKCR_3DCLKSEL_OFF	0x00000080	// For 3D internal Clock     100MHz  for 2ndCut
#define	VCRSYS_CLKCR_3DCLKSEL_ON	0x00000000	// For internal 3D Clock     50MHz   for 2ndCut
#define	VCRSYS_CLKCR_GPSCLKSTP_OFF	0x00000040	// For GPS Clock             OFF
#define	VCRSYS_CLKCR_GPSCLKSTP_ON	0x00000000	// For GPS Clock             ON
#define	VCRSYS_CLKCR_CLKSTP_OFF		0x00000020	// For Reserved Module Clock OFF
#define	VCRSYS_CLKCR_CLKSTP_ON		0x00000000	// For Reserved Module Clock ON
#define	VCRSYS_CLKCR_U1CLKSTPl_OFF	0x00000010	// For USB1.1 Clock          OFF
#define	VCRSYS_CLKCR_U1CLKSTPl_ON	0x00000000	// For USB1.1 Clock          ON
#define	VCRSYS_CLKCR_VINCLKCR_OFF	0x00000008	// For VIN Clock             OFF
#define	VCRSYS_CLKCR_VINCLKCR_ON	0x00000000	// For VIN Clock             ON
#define	VCRSYS_CLKCR_DUCLKSTP_OFF	0x00000004	// For DU Clock              OFF
#define	VCRSYS_CLKCR_DUCLKSTP_ON	0x00000000	// For DU Clock              ON
#define	VCRSYS_CLKCR_3DCLKSTP_OFF	0x00000002	// For 3D Clock              OFF
#define	VCRSYS_CLKCR_3DCLKSTP_ON	0x00000000	// For 3D Clock              ON
#define	VCRSYS_CLKCR_2DCLKSTP_OFF	0x00000001	// For 2D Clock              OFF
#define	VCRSYS_CLKCR_2DCLKSTP_ON	0x00000000	// For 2D Clock              ON

// Definitions for VCRSYS PMSR1
#define VCRSYS_PMSR1_IR5_IRQ5		0x00000000	//; IRQ5
#define VCRSYS_PMSR1_IR5_EX_CS7		0x10000000	//; EX_CS7

#define VCRSYS_PMSR1_IR4_IRQ4		0x00000000	//; IRQ4
#define VCRSYS_PMSR1_IR4_EX_CS6		0x08000000	//; EX_CS6

#define VCRSYS_PMSR1_IR3_IRQ3		0x00000000	//; IRQ3
#define VCRSYS_PMSR1_IR3_EX_CS5		0x04000000	//; EX_CS5

#define VCRSYS_PMSR1_IR2_IRQ2		0x00000000	//; IRQ2
#define VCRSYS_PMSR1_IR2_EX_WAIT2	0x02000000	//; EX_WAIT2

#define VCRSYS_PMSR1_IR1_IRQ1		0x00000000	//; IRQ1
#define VCRSYS_PMSR1_IR1_EX_WAIT1	0x01000000	//; EX_WAIT1

#define VCRSYS_PMSR1_EXA_EXBUS		0x00000000	//; EXBUS25-11
#define VCRSYS_PMSR1_EXA_GPIO		0x00040000	//; GPIO

#define VCRSYS_PMSR1_ATAPI_ATAPI	0x00000000	//; ATAPI
#define VCRSYS_PMSR1_ATAPI_GPIO		0x00010000	//; GPIO

#define VCRSYS_PMSR1_GPIO			0x00000000	//; Reserved

#define VCRSYS_PMSR1_EXD31_GPIO		0x00000000	//; GPIO
#define VCRSYS_PMSR1_EXD31_EXBUS	0x00004000	//; EXBUS

#define VCRSYS_PMSR1_EXD15_EXBUS	0x00000000	//; EXBUS
#define VCRSYS_PMSR1_EXD15_GPIO		0x00002000	//; GPIO

#define VCRSYS_PMSR1_EXCP_EXCS		0x00000000	//; EX_CS4

#define VCRSYS_PMSR1_EXCS1_EXCS		0x00000000	//; EX_CS1
#define VCRSYS_PMSR1_EXCS1_GPIO		0x00000100	//; GPIO

#define VCRSYS_PMSR1_EXCS0_EXCS		0x00000000	//; EX_CS0
#define VCRSYS_PMSR1_EXCS0_GPIO		0x00000080	//; GPIO

#define VCRSYS_PMSR1_CS1_CS			0x00000000	//; CS1
#define VCRSYS_PMSR1_CS1_GPIO		0x00000040	//; GPIO

#define VCRSYS_PMSR1_DREQ1_DREQ		0x00000000	//; DREQ1
#define VCRSYS_PMSR1_DREQ1_GPIO		0x00000020	//; GPIO

#define VCRSYS_PMSR1_DREQ0_DREQ		0x00000000	//; DREQ0
#define VCRSYS_PMSR1_DREQ0_GPIO		0x00000010	//; GPIO

#define VCRSYS_PMSR1_DACK1_DACK		0x00000000	//; DACK1
#define VCRSYS_PMSR1_DACK1_GPIO		0x00000008	//; GPIO

#define VCRSYS_PMSR1_DACK0_DACK		0x00000000	//; DACK0
#define VCRSYS_PMSR1_DACK0_GIPO		0x00000004	//; GPIO

#define VCRSYS_PMSR1_DRACK0_DRACK	0x00000000	//; DRACK0
#define VCRSYS_PMSR1_DRACK0_GPIO	0x00000002	//; GPIO