#define	VCRSYS_DCBR_CIT_LEVEL_DACK16_READ	0x00000280 << 6	// LEVEL DACK16(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK16_WRITE	0x00000284 << 6	// LEVEL DACK16(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK17_READ	0x00000288 << 6	// LEVEL DACK17(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK17_WRITE	0x0000028C << 6	// LEVEL DACK17(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK18_READ	0x00000290 << 6	// LEVEL DACK18(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK18_WRITE	0x00000294 << 6	// LEVEL DACK18(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK19_READ	0x00000298 << 6	// LEVEL DACK19(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK19_WRITE	0x0000029C << 6	// LEVEL DACK19(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK20_READ	0x000002A0 << 6	// LEVEL DACK20(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK20_WRITE	0x000002A4 << 6	// LEVEL DACK20(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK21_READ	0x000002A8 << 6	// LEVEL DACK21(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK21_WRITE	0x000002AC << 6	// LEVEL DACK21(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK22_READ	0x000002B0 << 6	// LEVEL DACK22(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK22_WRITE	0x000002B4 << 6	// LEVEL DACK22(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK23_READ	0x000002B8 << 6	// LEVEL DACK23(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK23_WRITE	0x000002BC << 6	// LEVEL DACK23(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK24_READ	0x000002C0 << 6	// LEVEL DACK24(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK24_WRITE	0x000002C4 << 6	// LEVEL DACK24(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK25_READ	0x000002C8 << 6	// LEVEL DACK25(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK25_WRITE	0x000002CC << 6	// LEVEL DACK25(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK26_READ	0x000002D0 << 6	// LEVEL DACK26(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK26_WRITE	0x000002D4 << 6	// LEVEL DACK26(Write)

#define	VCRSYS_DCBR_CIT_PULSE_DREQ0_READ	0x00000100 << 6	// PULSE DREQ0(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ0_WRITE	0x00000104 << 6	// PULSE DREQ0(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ1_READ	0x00000108 << 6	// PULSE DREQ1(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ1_WRITE	0x0000010C << 6	// PULSE DREQ1(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ2_READ	0x00000110 << 6	// PULSE DREQ2(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ2_WRITE	0x00000114 << 6	// PULSE DREQ2(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ3_READ	0x00000118 << 6	// PULSE DREQ3(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ3_WRITE	0x0000011C << 6	// PULSE DREQ3(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ4_READ	0x00000120 << 6	// PULSE DREQ4(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ4_WRITE	0x00000124 << 6	// PULSE DREQ4(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ5_READ	0x00000128 << 6	// PULSE DREQ5(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ5_WRITE	0x0000012C << 6	// PULSE DREQ5(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ6_READ	0x00000130 << 6	// PULSE DREQ6(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ6_WRITE	0x00000134 << 6	// PULSE DREQ6(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ7_READ	0x00000138 << 6	// PULSE DREQ7(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ7_WRITE	0x0000013C << 6	// PULSE DREQ7(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ8_READ	0x00000140 << 6	// PULSE DREQ8(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ8_WRITE	0x00000144 << 6	// PULSE DREQ8(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ9_READ	0x00000148 << 6	// PULSE DREQ9(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ9_WRITE	0x0000014C << 6	// PULSE DREQ9(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ10_READ	0x00000150 << 6	// PULSE DREQ10(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ10_WRITE	0x00000154 << 6	// PULSE DREQ10(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ11_READ	0x00000158 << 6	// PULSE DREQ11(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ11_WRITE	0x0000015C << 6	// PULSE DREQ11(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ12_READ	0x00000160 << 6	// PULSE DREQ12(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ12_WRITE	0x00000164 << 6	// PULSE DREQ12(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ13_READ	0x00000168 << 6	// PULSE DREQ13(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ13_WRITE	0x0000016C << 6	// PULSE DREQ13(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ14_READ	0x00000170 << 6	// PULSE DREQ14(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ14_WRITE	0x00000174 << 6	// PULSE DREQ14(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ15_READ	0x00000178 << 6	// PULSE DREQ15(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ15_WRITE	0x0000017C << 6	// PULSE DREQ15(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ16_READ	0x00000180 << 6	// PULSE DREQ16(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ16_WRITE	0x00000184 << 6	// PULSE DREQ16(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ17_READ	0x00000188 << 6	// PULSE DREQ17(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ17_WRITE	0x0000018C << 6	// PULSE DREQ17(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ18_READ	0x00000190 << 6	// PULSE DREQ18(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ18_WRITE	0x00000194 << 6	// PULSE DREQ18(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ19_READ	0x00000198 << 6	// PULSE DREQ19(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ19_WRITE	0x0000019C << 6	// PULSE DREQ19(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ20_READ	0x000001A0 << 6	// PULSE DREQ20(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ20_WRITE	0x000001A4 << 6	// PULSE DREQ20(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ21_READ	0x000001A8 << 6	// PULSE DREQ21(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ21_WRITE	0x000001AC << 6	// PULSE DREQ21(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ22_READ	0x000001B0 << 6	// PULSE DREQ22(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ22_WRITE	0x000001B4 << 6	// PULSE DREQ22(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ23_READ	0x000001B8 << 6	// PULSE DREQ23(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ23_WRITE	0x000001BC << 6	// PULSE DREQ23(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ24_READ	0x000001C0 << 6	// PULSE DREQ24(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ24_WRITE	0x000001C4 << 6	// PULSE DREQ24(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ25_READ	0x000001C8 << 6	// PULSE DREQ25(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ25_WRITE	0x000001CC << 6	// PULSE DREQ25(Write)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ26_READ	0x000001D0 << 6	// PULSE DREQ26(Read)
#define	VCRSYS_DCBR_CIT_PULSE_DREQ26_WRITE	0x000001D4 << 6	// PULSE DREQ26(Write)

#define	VCRSYS_DCBR_DUC_STOP		0x00000000	// PPC Curcuit STOP
#define	VCRSYS_DCBR_DUC_COUNT		0x00000008	// PPC Curcuit COUNT
#define	VCRSYS_DCBR_CMDS_TRIGER		0x00000000	// Count mode : Triger
#define	VCRSYS_DCBR_CMDS_DIRECT		0x00000000	// Count mode : Direct
#define	VCRSYS_DCBR_PPCE_DISABLE	0x00000000	// PPC Disable
#define	VCRSYS_DCBR_PPCE_ENABLE		0x00000001	// PPC Enable


// Definitions for VCRSYS ECPUCR
#define	VCRSYS_ECPUCR_ECPENB		0x00000002	// External CPU Connect 0:Disable 1:Enable
#define	VCRSYS_ECPUCR_ECPSEL		0x00000001	// External CPU Select  0:SH7751  1:SH7750

// Definitions for VCRSYS ECPUMR
#define	VCRSYS_ECPUIR_ECPINT		0x00000001	// Notice of Interrupts to INTC  0:Disable 1:Enable


//
// for Bus bridge
//     Definitions for BSC
//
#define	SH7770_BSC_REGBASE		(SH7770_BUSBRIDGE_BASE+SH7770_BSC_OFFSET)
#define	SH7770_BSC_REGSIZE		0x00000500

#define	BSC_CS0CTRL_OFFSET		0x00000000
#define	BSC_CS1CTRL_OFFSET		0x00000004
#define	BSC_ECS0CTRL_OFFSET		0x00000008
#define	BSC_ECS1CTRL_OFFSET		0x0000000C
#define	BSC_ECS2CTRL_OFFSET		0x00000010
#define	BSC_ECS3CTRL_OFFSET		0x00000014
#define	BSC_ECS4CTRL_OFFSET		0x00000018
#define	BSC_ECS5CTRL_OFFSET		0x0000001C
#define	BSC_ECS6CTRL_OFFSET		0x00000020
#define	BSC_ECS7CTRL_OFFSET		0x00000024
#define	BSC_CSWCR0_OFFSET		0x00000030
#define	BSC_CSWCR1_OFFSET		0x00000034
#define	BSC_ECSWCR0_OFFSET		0x00000038
#define	BSC_ECSWCR1_OFFSET		0x0000003C
#define	BSC_ECSWCR2_OFFSET		0x00000040
#define	BSC_ECSWCR3_OFFSET		0x00000044
#define	BSC_ECSWCR4_OFFSET		0x00000048
#define	BSC_ECSWCR5_OFFSET		0x0000004C
#define	BSC_ECSWCR6_OFFSET		0x00000050
#define	BSC_ECSWCR7_OFFSET		0x00000054
#define	BSC_DMAWCR0_OFFSET		0x00000058
#define	BSC_DMAWCR1_OFFSET		0x0000005C
#define	BSC_DMAWCR2_OFFSET		0x00000060
#define	BSC_DMAWCR3_OFFSET		0x00000064
#define	BSC_DMAWCR4_OFFSET		0x00000068
#define	BSC_CSPWCR0_OFFSET		0x00000070
#define	BSC_CSPWCR1_OFFSET		0x00000074
#define	BSC_ECSPWCR0_OFFSET		0x00000078
#define	BSC_ECSPWCR1_OFFSET		0x0000007C
#define	BSC_ECSPWCR2_OFFSET		0x00000080
#define	BSC_ECSPWCR3_OFFSET		0x00000084
#define	BSC_ECSPWCR4_OFFSET		0x00000088
#define	BSC_ECSPWCR5_OFFSET		0x0000008C
#define	BSC_ECSPWCR6_OFFSET		0x00000090
#define	BSC_ECSPWCR7_OFFSET		0x00000094
#define	BSC_EXWTSYNC_OFFSET		0x00000098
#define	BSC_CS0BSTCTL_OFFSET		0x000000A0
#define	BSC_CS0BTPH_OFFSET		0x000000A4
#define	BSC_CS1GDST_OFFSET		0x000000B0
#define	BSC_ECS0GDST_OFFSET		0x000000B4
#define	BSC_ECS1GDST_OFFSET		0x000000B8
#define	BSC_ECS2GDST_OFFSET		0x000000BC
#define	BSC_ECS3GDST_OFFSET		0x000000C0
#define	BSC_ECS4GDST_OFFSET		0x000000C4
#define	BSC_ECS5GDST_OFFSET		0x000000C8
#define	BSC_ECS6GDST_OFFSET		0x000000CC
#define	BSC_ECS7GDST_OFFSET		0x000000D0
#define	BSC_DMASET0_OFFSET		0x000000E0
#define	BSC_DMASET1_OFFSET		0x000000E4
#define	BSC_DMASET2_OFFSET		0x000000E8
#define	BSC_DMASET3_OFFSET		0x000000EC
#define	BSC_DMASET4_OFFSET		0x000000F0
#define	BSC_EXDMCR0_OFFSET		0x000000F4
#define	BSC_EXDMCR1_OFFSET		0x000000F8
#define	BSC_EXDMCR2_OFFSET		0x000000FC
#define	BSC_EXDMCR3_OFFSET		0x00000100
#define	BSC_EXDMCR4_OFFSET		0x00000104
#define	BSC_BCINTSR_OFFSET		0x00000120
#define	BSC_BCINTCR_OFFSET		0x00000124
#define	BSC_BCINTMR_OFFSET		0x00000128
#define	BSC_EXBATLV_OFFSET		0x00000130
#define	BSC_EXPIN_OFFSET		0x00000200
#define	BSC_EXPOUT_OFFSET		0x00000204

#define	BSC_CS0CTRL			(SH7770_BSC_REGBASE + BSC_CS0CTRL_OFFSET)
#define	BSC_CS1CTRL			(SH7770_BSC_REGBASE + BSC_CS1CTRL_OFFSET)
#define	BSC_ECS0CTRL			(SH7770_BSC_REGBASE + BSC_ECS0CTRL_OFFSET)
#define	BSC_ECS1CTRL			(SH7770_BSC_REGBASE + BSC_ECS1CTRL_OFFSET)
#define	BSC_ECS2CTRL			(SH7770_BSC_REGBASE + BSC_ECS2CTRL_OFFSET)
#define	BSC_ECS3CTRL			(SH7770_BSC_REGBASE + BSC_ECS3CTRL_OFFSET)
#define	BSC_ECS4CTRL			(SH7770_BSC_REGBASE + BSC_ECS4CTRL_OFFSET)
#define	BSC_ECS5CTRL			(SH7770_BSC_REGBASE + BSC_ECS5CTRL_OFFSET)
#define	BSC_ECS6CTRL			(SH7770_BSC_REGBASE + BSC_ECS6CTRL_OFFSET)
#define	BSC_ECS7CTRL			(SH7770_BSC_REGBASE + BSC_ECS7CTRL_OFFSET)
#define	BSC_CSWCR0			(SH7770_BSC_REGBASE + BSC_CSWCR0_OFFSET)
#define	BSC_CSWCR1			(SH7770_BSC_REGBASE + BSC_CSWCR1_OFFSET)
#define	BSC_ECSWCR0			(SH7770_BSC_REGBASE + BSC_ECSWCR0_OFFSET)
#define	BSC_ECSWCR1			(SH7770_BSC_REGBASE + BSC_ECSWCR1_OFFSET)
#define	BSC_ECSWCR2			(SH7770_BSC_REGBASE + BSC_ECSWCR2_OFFSET)
#define	BSC_ECSWCR3			(SH7770_BSC_REGBASE + BSC_ECSWCR3_OFFSET)
#define	BSC_ECSWCR4			(SH7770_BSC_REGBASE + BSC_ECSWCR4_OFFSET)
#define	BSC_ECSWCR5			(SH7770_BSC_REGBASE + BSC_ECSWCR5_OFFSET)
#define	BSC_ECSWCR6			(SH7770_BSC_REGBASE + BSC_ECSWCR6_OFFSET)
#define	BSC_ECSWCR7			(SH7770_BSC_REGBASE + BSC_ECSWCR7_OFFSET)
#define	BSC_DMAWCR0			(SH7770_BSC_REGBASE + BSC_DMAWCR0_OFFSET)
#define	BSC_DMAWCR1			(SH7770_BSC_REGBASE + BSC_DMAWCR1_OFFSET)
#define	BSC_DMAWCR2			(SH7770_BSC_REGBASE + BSC_DMAWCR2_OFFSET)
#define	BSC_DMAWCR3			(SH7770_BSC_REGBASE + BSC_DMAWCR3_OFFSET)
#define	BSC_DMAWCR4			(SH7770_BSC_REGBASE + BSC_DMAWCR4_OFFSET)
#define	BSC_CSPWCR0			(SH7770_BSC_REGBASE + BSC_CSPWCR0_OFFSET)
#define	BSC_CSPWCR1			(SH7770_BSC_REGBASE + BSC_CSPWCR1_OFFSET)
#define	BSC_ECSPWCR0			(SH7770_BSC_REGBASE + BSC_ECSPWCR0_OFFSET)
#define	BSC_ECSPWCR1			(SH7770_BSC_REGBASE + BSC_ECSPWCR1_OFFSET)
#define	BSC_ECSPWCR2			(SH7770_BSC_REGBASE + BSC_ECSPWCR2_OFFSET)
#define	BSC_ECSPWCR3			(SH7770_BSC_REGBASE + BSC_ECSPWCR3_OFFSET)
#define	BSC_ECSPWCR4			(SH7770_BSC_REGBASE + BSC_ECSPWCR4_OFFSET)
#define	BSC_ECSPWCR5			(SH7770_BSC_REGBASE + BSC_ECSPWCR5_OFFSET)
#define	BSC_ECSPWCR6			(SH7770_BSC_REGBASE + BSC_ECSPWCR6_OFFSET)
#define	BSC_ECSPWCR7			(SH7770_BSC_REGBASE + BSC_ECSPWCR7_OFFSET)
#define	BSC_EXWTSYNC			(SH7770_BSC_REGBASE + BSC_EXWTSYNC_OFFSET)
#define	BSC_CS0BSTCTL			(SH7770_BSC_REGBASE + BSC_CS0BSTCTL_OFFSET)
#define	BSC_CS0BTPH			(SH7770_BSC_REGBASE + BSC_CS0BTPH_OFFSET)
#define	BSC_CS1GDST			(SH7770_BSC_REGBASE + BSC_CS1GDST_OFFSET)
#define	BSC_ECS0GDST			(SH7770_BSC_REGBASE + BSC_ECS0GDST_OFFSET)
#define	BSC_ECS1GDST			(SH7770_BSC_REGBASE + BSC_ECS1GDST_OFFSET)
#define	BSC_ECS2GDST			(SH7770_BSC_REGBASE + BSC_ECS2GDST_OFFSET)
#define	BSC_ECS3GDST			(SH7770_BSC_REGBASE + BSC_ECS3GDST_OFFSET)
#define	BSC_ECS4GDST			(SH7770_BSC_REGBASE + BSC_ECS4GDST_OFFSET)
#define	BSC_ECS5GDST			(SH7770_BSC_REGBASE + BSC_ECS5GDST_OFFSET)
#define	BSC_ECS6GDST			(SH7770_BSC_REGBASE + BSC_ECS6GDST_OFFSET)
#define	BSC_ECS7GDST			(SH7770_BSC_REGBASE + BSC_ECS7GDST_OFFSET)
#define	BSC_DMASET0			(SH7770_BSC_REGBASE + BSC_DMASET0_OFFSET)
#define	BSC_DMASET1			(SH7770_BSC_REGBASE + BSC_DMASET1_OFFSET)
#define	BSC_DMASET2			(SH7770_BSC_REGBASE + BSC_DMASET2_OFFSET)
#define	BSC_DMASET3			(SH7770_BSC_REGBASE + BSC_DMASET3_OFFSET)
#define	BSC_DMASET4			(SH7770_BSC_REGBASE + BSC_DMASET4_OFFSET)
#define	BSC_EXDMCR0			(SH7770_BSC_REGBASE + BSC_EXDMCR0_OFFSET)
#define	BSC_EXDMCR1			(SH7770_BSC_REGBASE + BSC_EXDMCR1_OFFSET)
#define	BSC_EXDMCR2			(SH7770_BSC_REGBASE + BSC_EXDMCR2_OFFSET)
#define	BSC_EXDMCR3			(SH7770_BSC_REGBASE + BSC_EXDMCR3_OFFSET)
#define	BSC_EXDMCR4			(SH7770_BSC_REGBASE + BSC_EXDMCR4_OFFSET)
#define	BSC_BCINTSR			(SH7770_BSC_REGBASE + BSC_BCINTSR_OFFSET)
#define	BSC_BCINTCR			(SH7770_BSC_REGBASE + BSC_BCINTCR_OFFSET)
#define	BSC_BCINTMR			(SH7770_BSC_REGBASE + BSC_BCINTMR_OFFSET)
#define	BSC_EXBATLV			(SH7770_BSC_REGBASE + BSC_EXBATLV_OFFSET)
#define	BSC_EXPIN			(SH7770_BSC_REGBASE + BSC_EXPIN_OFFSET)
#define	BSC_EXPOUT			(SH7770_BSC_REGBASE + BSC_EXPOUT_OFFSET)

// Definitions for BSC CS0,1CTRL
#define	BSC_CSxCTRL_CSxSZ_16BIT			0x00000020	// AREAx Bus Width (16bit)
#define	BSC_CSxCTRL_CSxSZ_8BIT			0x00000010	// AREAx Bus Width  (8bit)
#define	BSC_CSxCTRL_CSxSZ_32BIT			0x00000030	// AREAx Bus Width (32bit)
#define	BSC_CSxCTRL_CSxIF_STANDARD		0x00000000	// AREAx Bus I/F   (STANDARD/SRAM)
#define	BSC_CSxCTRL_CSxIF_BURSTROM		0x00000001	// AREAx Bus I/F   (BurstROM)

// Definitions for BSC ECSxCTRL(x=0,1,2,3,4,5,6,7)
#define	BSC_ECSxCTRL_ECSxCP_1M			0x00000100	// External Areax Capacity (1MByte)
#define	BSC_ECSxCTRL_ECSxCP_8M			0x00000800	// External Areax Capacity (8MByte)
#define	BSC_ECSxCTRL_ECSxCP_64M			0x00004000	// External Areax Capacity (64MByte)
#define	BSC_ECSxCTRL_ECSxSZ_16BIT		0x00000020	// External Areax Bus Width (16bit)
#define	BSC_ECSxCTRL_ECSxSZ_8BIT		0x00000010	// External Areax Bus Width ( 8bit)
#define	BSC_ECSxCTRL_ECSxSZ_32BIT		0x00000030	// External Areax Bus Width (32bit)
#define	BSC_ECSxCTRL_ECSxIF_STANDARD	0x00000000	// External Areax Bus I/F (STANDARD/SRAM)
#define	BSC_ECSxCTRL_ECSxIF_ATA			0x00000002	// External Areax Bus I/F (ATA)

// Definitions for BSC CSWCR0/1, ECSWCRx, EXDMWCRy

#define	BSC_CSWCR_WRSETUP_7		0x07000000	// write CS setup cycle
#define	BSC_CSWCR_WRSETUP_6		0x06000000
#define	BSC_CSWCR_WRSETUP_5		0x05000000
#define	BSC_CSWCR_WRSETUP_4		0x04000000
#define	BSC_CSWCR_WRSETUP_3		0x03000000
#define	BSC_CSWCR_WRSETUP_2		0x02000000
#define	BSC_CSWCR_WRSETUP_1		0x01000000
#define	BSC_CSWCR_WRSETUP_0		0x00000000

#define	BSC_CSWCR_WRHOLD_7		0x00700000	// write CS hold cycle
#define	BSC_CSWCR_WRHOLD_6		0x00600000
#define	BSC_CSWCR_WRHOLD_5		0x00500000
#define	BSC_CSWCR_WRHOLD_4		0x00400000
#define	BSC_CSWCR_WRHOLD_3		0x00300000
#define	BSC_CSWCR_WRHOLD_2		0x00200000
#define	BSC_CSWCR_WRHOLD_1		0x00100000
#define	BSC_CSWCR_WRHOLD_0		0x00000000