?? dma.h
字號:
//
// Copyright(C) Renesas Technology Corp. 2002-2003. All rights reserved.
//
// Bus Bridge DMA Utilities for ITS-DS7
//
// FILE : dma.h
// CREATED : 2002.02.25
// MODIFIED : 2003.07.02
// AUTHOR : Renesas Technology Corp.
// HARDWARE : RENESAS ITS-DS7
// HISTORY :
// 2003.07.02
// - Created release code.
// (based on WaveDev driver for ITS-DS4 Ver.2.2.0 for WCE4.1)
//
// SH7770 Define
// Ch0 -Ch10 use for HAC, HSSI, HSPDIF, SRC
// Ch11-Ch22 use for SCIF0-SCIF9
// Ch23 use for YUV <-> UM
// Ch24-Ch25 use for USB Function <-> UM
// Ch27-Ch31 use for Ex Device <-> UM
// ITS-DS7 Define
// HAC Ch0,1
// HSPDIF Ch2,3
// HSSI Ch4,5,6,7
// SRC Ch8,9
// SCIF0 Ch11,12 (Product Serial)
// SCIF3 Ch15,16 (IrDA)
// DMAC Ch number
#define CH_TX_HAC 0
#define CH_RX_HAC 1
#define CH_TX_HSPDIF 2
#define CH_RX_HSPDIF 3
#define CH_TX_HSSI_1 4
#define CH_RX_HSSI_1 5
#define CH_TX_HSSI_2 6
#define CH_RX_HSSI_2 7
#define CH_TX_SRC 8
#define CH_RX_SRC 9
#define CH_TX_SCIF0 11
#define CH_RX_SCIF0 12
#define CH_TX_SCIF3 15
#define CH_RX_SCIF3 16
// DSAR0 DMA Source Address reg 0
#define DSAR0_DSA 0xFFFFFFFD // DMA source address 0
#define DSAR0_MASK DSAR0_DSA
// DDAR0 DMA Destination Address reg 0
#define DDAR0_DDA 0xFFFFFFFD // DMA destination address 0
#define DDAR0_MASK DDAR0_DSA
// DTCR0 DMA Transfer Count Reg 0
#define DTCR0_DTC 0x000FFFFF // DMA transfer count 0
#define DTCR0_MASK DTCR0_DTC
// DSAR0 DMA Source Address reg 0
#define DSAR1_DSA 0xFFFFFFFD // DMA sourceaddress 1
#define DSAR1_MASK DSAR1_DSA
// DDAR0 DMA Destination Address reg 0
#define DDAR1_DDA 0xFFFFFFFD // DMA destination address 1
#define DDAR1_MASK DDAR1_DSA
// DTCR0 DMA Transfer Count Reg 0
#define DTCR1_DTC 0x000FFFFF // DMA transfer count 0
#define DTCR1_MASK DTCR1_DTC
// DMA Source Address Status reg
#define DSASR_DSAS 0xFFFFFFFF // DMA source address status
#define DSASR_MASK DSASR_DSAS
// DMA Destination Address Status reg
#define DDASR_DDAS 0xFFFFFFFF // DMA destination address status
#define DDASR_MASK DDASR_DDAS
// DMA Transfer Count Status reg
#define DTCSR_DTCS 0x000FFFFF // Remaining number of DMA transfer
#define DTCSR_MASK DTCSR_DTCS
// DMA Port Select Reg
#define DPTR_SDPT 0x00000F00 // Source PDMA Port Select
#define DPTR_DDPT 0x0000000F // Destination PDMA Port Select
#define DPTR_MASK (DPTR_SDPT | DPTR_DDPT)
#define DPTR_SDPT_HAC 0x00000000 // Ch0-Ch10
#define DPTR_SDPT_HSPDIF 0x00000100
#define DPTR_SDPT_HSSI0 0x00000200
#define DPTR_SDPT_HSSI1 0x00000300
#define DPTR_SDPT_HSSI2 0x00000400
#define DPTR_SDPT_HSSI3 0x00000500
#define DPTR_SDPT_SRC 0x00000B00
#define DPTR_SDPT_SCIF0 0x00000000 // Ch11-Ch22
#define DPTR_SDPT_SCIF1 0x00000100
#define DPTR_SDPT_SCIF2 0x00000200
#define DPTR_SDPT_SCIF3 0x00000300
#define DPTR_SDPT_SCIF4 0x00000400
#define DPTR_SDPT_SCIF5 0x00000500
#define DPTR_SDPT_SCIF6 0x00000600
#define DPTR_SDPT_SCIF7 0x00000700
#define DPTR_SDPT_SCIF8 0x00000800
#define DPTR_SDPT_SCIF9 0x00000900
#define DPTR_DDPT_HAC 0x00000000 // Ch0-Ch10
#define DPTR_DDPT_HSPDIF 0x00000001
#define DPTR_DDPT_HSSI0 0x00000002
#define DPTR_DDPT_HSSI1 0x00000003
#define DPTR_DDPT_HSSI2 0x00000004
#define DPTR_DDPT_HSSI3 0x00000005
#define DPTR_DDPT_SRC 0x0000000B
#define DPTR_DDPT_SCIF0 0x00000000 // Ch11-Ch22
#define DPTR_DDPT_SCIF1 0x00000001
#define DPTR_DDPT_SCIF2 0x00000002
#define DPTR_DDPT_SCIF3 0x00000003
#define DPTR_DDPT_SCIF4 0x00000004
#define DPTR_DDPT_SCIF5 0x00000005
#define DPTR_DDPT_SCIF6 0x00000006
#define DPTR_DDPT_SCIF7 0x00000007
#define DPTR_DDPT_SCIF8 0x00000008
#define DPTR_DDPT_SCIF9 0x00000009
// DCR DMA Control reg ( * : Initial Value)
#define DCR_DPDS_8BIT 0x00000000 // Dst Bus width 8bit
#define DCR_DPDS_16BIT 0x00000001 // Dst Bus width 16bit
#define DCR_DPDS_32BIT 0x00000002 // Dst Bus width 32bit
#define DCR_DDRMD_MODULE 0x00000000 // Dst DMA Module Request Mode
#define DCR_DDRMD_AUTO 0x00000004 // Dst DMA Auto Request Mode
#define DCR_DDRMD_TIMER 0x00000008 // Dst DMA Timer Request Mode
#define DCR_DPDAM_FIX 0x00000000 // Dst Module Fix Address Mode
#define DCR_DPDAM_INCREMENT 0x00000010 // Dst Module Increment Address Mode
#define DCR_DMDL_MEMORY 0x00000000 // Dst Module Memory Select
#define DCR_DMDL_PERIPHERAL 0x00000020 // Dst Module Peripheral Select
#define DCR_SPDS_8BIT 0x00000000 // Src Bus width 8bit
#define DCR_SPDS_16BIT 0x00000100 // Src Bus width 16bit
#define DCR_SPDS_32BIT 0x00000200 // Src Bus width 32bit
#define DCR_SDRMD_MODULE 0x00000000 // Src DMA Request Module Request Mode
#define DCR_SDRMD_AUTO 0x00000400 // Src DMA Request Auto Request Mode
#define DCR_SDRMD_TIMER 0x00000800 // Src DMA Request Timer Request Mode
#define DCR_SPDAM_FIX 0x00000000 // Src Module Fix Address Mode
#define DCR_SPDAM_INCREMENT 0x00001000 // Src Module Increment Address Mode
#define DCR_SMDL_MEMORY 0x00000000 // Src Module Memory Select
#define DCR_SMDL_PERIPHERAL 0x00002000 // Src Module Peripheral Select
#define DCR_DIP_1PAGE 0x00000000 // DMA Infomation 1 Page Buffer Mode
#define DCR_DIP_2PAGE 0x00010000 // DMA Infomation 2 Page Buffer Mode
#define DCR_ACMD_DISABLE 0x00000000 // Auto Continuous Mode Disable
#define DCR_ACMD_ENABLE 0x00020000 // Auto Continuous Mode Enable
#define DCR_CT_DISABLE 0x00000000 // Continuous Transfer Mode Disable
#define DCR_CT_ENABLE 0x00040000 // Continuous Transfer Mode Enable
#define DCR_PKMD_DISABLE 0x00000000 // Data Packing Mode Disable
#define DCR_PKMD_ENABLE 0x00100000 // Data Packing Mode Enable
#define DCR_BTMD_DISABLE 0x00000000 // Burst Mode Burst Disable
#define DCR_BTMD_ENABLE 0x00200000 // Burst Mode Burst Enable
#define DCR_DTAU_BYTE 0x00000000 // DMA Data Alignment Transfer Unit Byte
#define DCR_DTAU_WORD 0x01000000 // DMA Data Alignment Transfer Unit Word
#define DCR_DTAC_DISABLE 0x00000000 // DMA Data Alignment Transfer Disable
#define DCR_DTAC_ENABLE 0x02000000 // DMA Data Alignment Transfer Enable
#define DCR_DTAMD_PIN 0x00000000 // DMA Data Alignment Transfer Mode PIN+PDS
#define DCR_DTAMD_DTAC 0x04000000 // DMA Data Alignment Transfer Mode DTAC+DTAU
// DCMDR DMA Command reg
#define DCMDR_DMEN 0x00000001 // DMA enable
#define DCMDR_DNXT 0x00000002 // DMA next transfer request
#define DCMDR_DQEND 0x00000004 // DMA conitnuous transfer finish
#define DCMDR_DMSPC 0x00000008 // DMA restart for bus cycle
#define DCMDR_DMSPD 0x00000010 // DMA pause for bus cycle
#define DCMDR_DQSPC 0x00000020 // DMA restart for unit
#define DCMDR_DQSPD 0x00000040 // DMA pause for unit
#define DCMDR_BDOUT 0x00000080 // DMA data force write
#define DCMDR_MASK (DCMDR_DMEN|DCMDR_DNXT|DCMDR_DQEND|DCMDR_DMSPC|DCMDR_DMSPD|DCMDR_DQSPC|DCMDR_DQSPD|DCMDR_BDOUT)
// DMSTP DMA Stop reg
#define DSTPR_DMSTP 0x00000001
#define DSTPR_MASK DSTPR_DMSTP
// DSTSR DMA Status reg
#define DSTSR_DMSTS 0x00000001 // DMA status
#define DSTSR_DRSTS 0x00000002 // DMA request status
#define DSTSR_DQSTS 0x00000004 // DMA queue status
#define DSTSR_DMSPS 0x00000008 // DMA pause status
#define DSTSR_DQSPS 0x00000010 // DMA pause for page unit
#define DSTSR_NDP0 0x00000020 // Next DMA page status 0
#define DSTSR_NDP1 0x00000040 // Next DMA page status 1
#define DSTSR_MASK (DSTSR_DMSTS|DSTSR_DRSTS|DSTSR_DQSTS|DSTSR_DMSPS|DSTSR_DQSPS|DSTSR_NDP0|DSTSR_NDP1)
// DTIMR DMA Timer Control reg
#define DTIMR_DTIM 0x0000FFFF
#define DTIMR_MASK DTIMR_DTIM
// DRMSKR Ex DMA Request Mask Control Reg
#define DRMSKR_DRMSK0 0x0000000F // Ex DMAC0 Request Cycle
#define DRMSKR_DRMSK1 0x000000F0 // Ex DMAC1 Request Cycle
#define DRMSKR_DRMSK2 0x00000F00 // Ex DMAC2 Request Cycle
#define DRMSKR_DRMSK3 0x0000F000 // Ex DMAC3 Request Cycle
#define DRMSKR_DRMSK4 0x000F0000 // Ex DMAC4 Request Cycle
// DMLVLR Ex DMA Memory Access Priority Level Control Reg
#define DMLVLR_DRMSK0_LV3 0x00000000 // ExDMAC0 LEVEL3
#define DMLVLR_DRMSK0_LV1 0x00000001 // ExDMAC0 LEVEL1
#define DMLVLR_DRMSK1_LV3 0x00000000 // ExDMAC1 LEVEL3
#define DMLVLR_DRMSK1_LV1 0x00000002 // ExDMAC1 LEVEL1
#define DMLVLR_DRMSK2_LV3 0x00000000 // ExDMAC2 LEVEL3
#define DMLVLR_DRMSK2_LV1 0x00000004 // ExDMAC2 LEVEL1
#define DMLVLR_DRMSK3_LV3 0x00000000 // ExDMAC3 LEVEL3
#define DMLVLR_DRMSK3_LV1 0x00000008 // ExDMAC3 LEVEL1
#define DMLVLR_DRMSK4_LV3 0x00000000 // ExDMAC4 LEVEL3
#define DMLVLR_DRMSK4_LV1 0x00000010 // ExDMAC4 LEVEL1
// DINTSR DMA Transfer-End Intr Diagnostic reg
#define DINTSR_DTE0 0x00000001
#define DINTSR_DTE31 0x80000000
// DINTCR DMA Transfer-End Intr Clear reg
#define DINTCR_DTEC0 0x00000001
#define DINTCR_DTEC31 0x80000000
// DINTMR DMA Transfer-End Intr Enable reg
#define DINTMR_DTEM0 0x00000001
#define DINTMR_DTEM31 0x80000000
// DACTSR DMA Active Status Reg
#define DACTSR_DS0 0x00000001
#define DACTSR_DS31 0x80000000
// SRSTR0 DMA Soft Reset reg
#define SRSTR0_SRST 0x00000001
typedef union _DMAC_DPTR {
struct {
DWORD DDPT :4 ;
DWORD PAD0 :4 ;
DWORD SDPT :4 ;
DWORD PAD1 :20 ;
}bits;
DWORD AsDWORD;
} DMAPortReg;
#define SDPT_HAC 0x0 // Ch0-Ch10
#define SDPT_HSPDIF 0x1
#define SDPT_HSSI0 0x2
#define SDPT_HSSI1 0x3
#define SDPT_HSSI2 0x4
#define SDPT_HSSI3 0x5
#define SDPT_SRC 0xB
#define SDPT_SCIF0 0x0 // Ch11-Ch22
#define SDPT_SCIF1 0x1
#define SDPT_SCIF2 0x2
#define SDPT_SCIF3 0x3
#define SDPT_SCIF4 0x4
#define SDPT_SCIF5 0x5
#define SDPT_SCIF6 0x6
#define SDPT_SCIF7 0x7
#define SDPT_SCIF8 0x8
#define SDPT_SCIF9 0x9
#define DDPT_HAC 0x0 // Ch0-Ch10
#define DDPT_HSPDIF 0x1
#define DDPT_HSSI0 0x2
#define DDPT_HSSI1 0x3
#define DDPT_HSSI2 0x4
#define DDPT_HSSI3 0x5
#define DDPT_SRC 0xB
#define DDPT_SCIF0 0x0 // Ch11-Ch22
#define DDPT_SCIF1 0x1
#define DDPT_SCIF2 0x2
#define DDPT_SCIF3 0x3
#define DDPT_SCIF4 0x4
#define DDPT_SCIF5 0x5
#define DDPT_SCIF6 0x6
#define DDPT_SCIF7 0x7
#define DDPT_SCIF8 0x8
#define DDPT_SCIF9 0x9
typedef union _DMAC_DCR {
struct {
DWORD DPDS :2 ; // Dst Bus Width. 8,16,32bit
DWORD DDRMD :2 ; // Dst DMA Request Mode. Module, Auto, Timer
DWORD DPDAM :1 ; // Dst Module Address Mode. Fix, Increment
DWORD DMDL :1 ; // Dst Module Select. Memory, Peripheral
DWORD PAD0 :2 ;
DWORD SPDS :2 ; // Src Bus Width. 8,16,32bit
DWORD SDRMD :2 ; // Src DMA Request Mode. Module, Auto, Timer
DWORD SPDAM :1 ; // Src Module Address Mode. Fix, Increment
DWORD SMDL :1 ; // Src Module Select. Memory, Peripheral
DWORD PAD1 :2 ;
DWORD DIP :1 ; // DMA Info Buffer Mode. 1Page Buffer, 2Page Buffer
DWORD ACMD :1 ; // Auto Continuous Mode. Disable, Enable
DWORD CT :1 ; // Continuous Transfer Mode. Disable, Enable
DWORD PAD2 :1 ;
DWORD PKMD :1 ; // Data Packing Mode. Disable, Enable
DWORD BTMD :1 ; // Burst Mode. Burst Disable, Burst Enable
DWORD PAD3 :2 ;
DWORD DTAU :1 ; // DMA Data Alignment Transfer Unit. Byte, Word
DWORD DTAC :1 ; // DMA Data Alignment Transfer Control. Disable, Enable
DWORD DTAMD :1 ; // DMA Data Alignment Transfer Mode PIN+PDS, DTAC+DTAU
DWORD PAD4 :5 ;
}bits;
DWORD AsDWORD;
} DMAControlReg;
#define PDS_8BIT 0x00
#define PDS_16BIT 0x01
#define PDS_32BIT 0x02
#define DRMD_MODULE 0x00
#define DRMD_AUTO 0x01
#define DRMD_TIMER 0x10
#define PDAM_FIX 0x0
#define PDAM_INCREMENT 0x1
#define MDL_MEMORY 0x0
#define MDL_PERIPHERAL 0x1
#define DIP_1PAGE 0x0
#define DIP_2PAGE 0x1
#define ACMD_DISABLE 0x0
#define ACMD_ENABLE 0x1
#define CT_DISABLE 0x0
#define CT_ENABLE 0x1
#define PKMD_DISABLE 0x0
#define PKMD_ENABLE 0x1
#define BTMD_DISABLE 0x0
#define BTMD_ENABLE 0x1
#define DTAU_BYTE 0x0
#define DTAU_WORD 0x1
#define DTAC_DISABLE 0x0
#define DTAC_ENABLE 0x1
#define DTAMD_PIN 0x0
#define DTAMD_DTAC 0x1
typedef union _DMAC_DCMDR {
struct {
DWORD DMEN :1; // DMA enable
DWORD DNXT :1; // DMA next transfer request
DWORD DQEND :1; // DMA conitnuous transfer finish
DWORD DMSPC :1; // DMA restart for bus cycle
DWORD DMSPD :1; // DMA pause for bus cycle
DWORD DQSPC :1; // DMA restart for unit
DWORD DQSPD :1; // DMA pause for unit
DWORD BDOUT :1; // DMA data force write
DWORD PAD :24;
}bits;
DWORD AsDWORD;
}DMACommandReg;
typedef union _DMAC_DSTSR {
struct {
DWORD DMSTS :1; // DMA status
DWORD DRSTS :1; // DMA request status
DWORD DQSTS :1; // DMA queue status
DWORD DMSPS :1; // DMA pause status
DWORD DQSPS :1; // DMA pause for page unit
DWORD NDP0 :1; // Next DMA page status 0
DWORD NDP1 :1; // Next DMA page status 1
DWORD PAD :25;
}bits;
DWORD AsDWORD;
}DMAStatusReg;
typedef struct _DMA_INFO {
DWORD Ch; // DMA Channel
PVULONG pvRegBase; // Register Base Address
PVULONG pvDSAR0; // Page0 Source Address Reg
PVULONG pvDDAR0; // Page0 Destination Address Reg
PVULONG pvDTCR0; // Page0 Transfer Count Reg
PVULONG pvDSAR1; // Page1 Source Address Reg
PVULONG pvDDAR1; // Page1 Destination Address Reg
PVULONG pvDTCR1; // Page1 Transfer Count Reg
PVULONG pvDSASR; // Source Address Status Reg
PVULONG pvDDASR; // Destination Address Status Reg
PVULONG pvDTCSR; // Transfer Count Status Reg
PVULONG pvDPTR; // Port Select Reg
PVULONG pvDCR; // Control Reg
PVULONG pvDCMDR; // Command Reg
PVULONG pvDSTPR; // Force Terminate Reg
PVULONG pvDSTSR; // Status Reg
PVULONG pvDTIMR; // Timer Control Reg
PVULONG pvDRMSKR; // ExDMA Request Mask Control Reg
PVULONG pvDMLVLR; // ExDMA Memory Access Priority Level Control Reg
PVULONG pvDINTSR; // Transfer Intr Status Reg
PVULONG pvDINTCR; // Transfer Intr Clear Reg
PVULONG pvDINTMR; // Transfer Intr Enable Reg
PVULONG pvDACTSR; // DMA Active Status Reg
PVULONG pvSRSTR; // Channel Software Reset Reg
} DMA_INFO, *PDMA_INFO;
BOOL dma_Init(int Ch, PDMA_INFO *pRetDmaInfo);
BOOL dma_Deinit(PDMA_INFO pDmaInfo);
BOOL dma_SetPage(PDMA_INFO pDmaInfo, DWORD PageNum, DWORD SrcAddr, DWORD DstAddr, DWORD Size);
BOOL dma_SetControl(PDMA_INFO pDmaInfo, DWORD DCR);
BOOL dma_SetCommand(PDMA_INFO pDmaInfo, DWORD DCMDR);
BOOL dma_SetPort(PDMA_INFO pDmaInfo, DWORD DPTR);
BOOL dma_InterruptEnable(PDMA_INFO pDmaInfo);
BOOL dma_InterruptDisable(PDMA_INFO pDmaInfo);
BOOL dma_Stop(PDMA_INFO pDmaInfo);
//BOOL dma_IsFinished(PDMA_INFO pDmaInfo, DWORD DINTSR);
BOOL dma_IsFinished(PDMA_INFO pDmaInfo);
BOOL dma_InterruptClear(PDMA_INFO pDmaInfo);
#define dma_TxStart(pDmaInfo) dma_SetCommand(pDmaInfo, (DCMDR_DMEN | DCMDR_DNXT) );
#define dma_TxContinue(pDmaInfo) dma_SetCommand(pDmaInfo, DCMDR_DNXT) );
#define dma_TxFinish(pDmaInfo) dma_SetCommand(pDmaInfo, DCMDR_DQEND) );
#define dma_RxStart(pDmaInfo) dma_SetCommand(pDmaInfo, (DCMDR_DMEN | DCMDR_DNXT)) );
#define dma_RxContinue(pDmaInfo) dma_SetCommand(pDmaInfo, DCMDR_DNXT) );
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -