?? sh7770.inc
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; Copyright(C) Renesas Technology Corp. 2003-2004. All rights reserved.
;
; header file for ITS-DS7 Ver.1.0.0
;
; FILE : SH7770.inc
; CREATED : 2003.06.20
; MODIFIED : 2004.12.28
; AUTHOR : Renesas Technology Corp.
; HARDWARE : RENESAS ITS-DS7
; HISTORY :
; 2003.06.20
; - Created release code.
; 2003.11.21
; - Names of register definition are changed.
; 2004.03.04
; - Deleted SH7770_2NDCUT.
; 2004.03.10
; - Modified TMU345,TMU678 register offset.
; 2004.03.12
; - Modified EMI_MIM_SETUP2 DRE disable.
; 2004.04.09
; - Modified 0x to h'.
; - Modified Revival 2NDCUT for setting of CPUOPM.
; - Modified change MIM define value.
; 2004.04.12
; - Modified FRQCR register setting value was corrected.(Ex-Bus = 50MHz)
; 2004.05.19
; - Modified FRQCR define.
; 2004.09.01
; - Created release code for WCE5.0.
; 2004.12.28
; - Modified INTC_USERIMASK.
;// define for CHIP REVISION
SH7770_1STCUT .equ 1
SH7770_2NDCUT .equ 2
SH7770_FINALCUT .equ 99
;
; SH7770 Chip module offsets (AREA7)
;
DUMMY_OFFSET .equ h'00000000 ;// for debug
SH7770_DEBUG_OFFSET .equ h'00000000
SH7770_DEBUG_BASE .equ (AREA_7+DUMMY_OFFSET + SH7770_DEBUG_OFFSET)
SH7770_MBX_OFFSET .equ h'01000000
SH7770_MBX_BASE .equ (AREA_7+DUMMY_OFFSET + SH7770_MBX_OFFSET)
SH7770_SHWYDMAC_OFFSET .equ h'02000000
SH7770_SHWYDMAC_BASE .equ (AREA_7+DUMMY_OFFSET + SH7770_SHWYDMAC_OFFSET)
SH7770_EMI_OFFSET .equ h'02800000
SH7770_EMI_BASE .equ (AREA_7+DUMMY_OFFSET + SH7770_EMI_OFFSET)
SH7770_COREERR_OFFSET .equ h'03000000
SH7770_COREERR_BASE .equ (AREA_7+DUMMY_OFFSET + SH7770_COREERR_OFFSET)
SH7770_COREUBC_OFFSET .equ h'03200000
SH7770_COREUBC_BASE .equ (AREA_7+DUMMY_OFFSET + SH7770_COREUBC_OFFSET)
SH7770_SHWYROUTER_OFFSET .equ h'03400000
SH7770_SHWYROUTER_BASE .equ (AREA_7+DUMMY_OFFSET + SH7770_SHWYROUTER_OFFSET)
SH7770_BUSBRIDGE_OFFSET .equ h'03800000
SH7770_BUSBRIDGE_BASE .equ (AREA_7+DUMMY_OFFSET + SH7770_BUSBRIDGE_OFFSET)
;
; EMI ( MCU ) Memory Controller
;
EMI_VCR_OFFSET .equ h'0000
EMI_MIM_OFFSET .equ h'0008
EMI_SCR_OFFSET .equ h'0010
EMI_STR_OFFSET .equ h'0018
EMI_SDRA_OFFSET .equ h'0030
;EMI_SDMR_OFFSET .equ h'0000
EMI_LTC0_OFFSET .equ h'0100
EMI_LTAD0_OFFSET .equ h'0108
EMI_LTAM0_OFFSET .equ h'0110
EMI_LTC1_OFFSET .equ h'0118
EMI_LTAD1_OFFSET .equ h'0120
EMI_LTAM1_OFFSET .equ h'0128
EMI_LTC2_OFFSET .equ h'0130
EMI_LTAD2_OFFSET .equ h'0138
EMI_LTAM2_OFFSET .equ h'0140
EMI_LTC3_OFFSET .equ h'0148
EMI_LTAD3_OFFSET .equ h'0150
EMI_LTAM3_OFFSET .equ h'0158
EMI_LTC4_OFFSET .equ h'0160
EMI_LTAD4_OFFSET .equ h'0168
EMI_LTAM4_OFFSET .equ h'0170
EMI_LTC5_OFFSET .equ h'0178
EMI_LTAD5_OFFSET .equ h'0180
EMI_LTAM5_OFFSET .equ h'0188
EMI_LTC6_OFFSET .equ h'0190
EMI_LTAD6_OFFSET .equ h'0198
EMI_LTAM6_OFFSET .equ h'01A0
EMI_LTC7_OFFSET .equ h'01A8
EMI_LTAD7_OFFSET .equ h'01B0
EMI_LTAM7_OFFSET .equ h'01B8
EMI_DBK_OFFSET .equ h'0400
EMI_VCR_HIGH .equ (SH7770_EMI_BASE + EMI_VCR_OFFSET)
EMI_MIM_HIGH .equ (SH7770_EMI_BASE + EMI_MIM_OFFSET)
EMI_SCR_HIGH .equ (SH7770_EMI_BASE + EMI_SCR_OFFSET)
EMI_STR_HIGH .equ (SH7770_EMI_BASE + EMI_STR_OFFSET)
EMI_SDRA_HIGH .equ (SH7770_EMI_BASE + EMI_SDRA_OFFSET)
;EMI_SDMR_HIGH .equ (SH7770_EMI_BASE + EMI_SDMR_OFFSET)
EMI_LTC0_HIGH .equ (SH7770_EMI_BASE + EMI_LTC0_OFFSET)
EMI_LTAD0_HIGH .equ (SH7770_EMI_BASE + EMI_LTAD0_OFFSET)
EMI_LTAM0_HIGH .equ (SH7770_EMI_BASE + EMI_LTAM0_OFFSET)
EMI_LTC1_HIGH .equ (SH7770_EMI_BASE + EMI_LTC1_OFFSET)
EMI_LTAD1_HIGH .equ (SH7770_EMI_BASE + EMI_LTAD1_OFFSET)
EMI_LTAM1_HIGH .equ (SH7770_EMI_BASE + EMI_LTAM1_OFFSET)
EMI_LTC2_HIGH .equ (SH7770_EMI_BASE + EMI_LTC2_OFFSET)
EMI_LTAD2_HIGH .equ (SH7770_EMI_BASE + EMI_LTAD2_OFFSET)
EMI_LTAM2_HIGH .equ (SH7770_EMI_BASE + EMI_LTAM2_OFFSET)
EMI_LTC3_HIGH .equ (SH7770_EMI_BASE + EMI_LTC3_OFFSET)
EMI_LTAD3_HIGH .equ (SH7770_EMI_BASE + EMI_LTAD3_OFFSET)
EMI_LTAM3_HIGH .equ (SH7770_EMI_BASE + EMI_LTAM3_OFFSET)
EMI_LTC4_HIGH .equ (SH7770_EMI_BASE + EMI_LTC4_OFFSET)
EMI_LTAD4_HIGH .equ (SH7770_EMI_BASE + EMI_LTAD4_OFFSET)
EMI_LTAM4_HIGH .equ (SH7770_EMI_BASE + EMI_LTAM4_OFFSET)
EMI_LTC5_HIGH .equ (SH7770_EMI_BASE + EMI_LTC5_OFFSET)
EMI_LTAD5_HIGH .equ (SH7770_EMI_BASE + EMI_LTAD5_OFFSET)
EMI_LTAM5_HIGH .equ (SH7770_EMI_BASE + EMI_LTAM5_OFFSET)
EMI_LTC6_HIGH .equ (SH7770_EMI_BASE + EMI_LTC6_OFFSET)
EMI_LTAD6_HIGH .equ (SH7770_EMI_BASE + EMI_LTAD6_OFFSET)
EMI_LTAM6_HIGH .equ (SH7770_EMI_BASE + EMI_LTAM6_OFFSET)
EMI_LTC7_HIGH .equ (SH7770_EMI_BASE + EMI_LTC7_OFFSET)
EMI_LTAD7_HIGH .equ (SH7770_EMI_BASE + EMI_LTAD7_OFFSET)
EMI_LTAM7_HIGH .equ (SH7770_EMI_BASE + EMI_LTAM7_OFFSET)
EMI_DBK_HIGH .equ (SH7770_EMI_BASE + EMI_DBK_OFFSET)
EMI_VCR_LOW .equ (SH7770_EMI_BASE + EMI_VCR_OFFSET + h'04)
EMI_MIM_LOW .equ (SH7770_EMI_BASE + EMI_MIM_OFFSET + h'04)
EMI_SCR_LOW .equ (SH7770_EMI_BASE + EMI_SCR_OFFSET + h'04)
EMI_STR_LOW .equ (SH7770_EMI_BASE + EMI_STR_OFFSET + h'04)
EMI_SDRA_LOW .equ (SH7770_EMI_BASE + EMI_SDRA_OFFSET + h'04)
;EMI_SDMR_LOW .equ (SH7770_EMI_BASE + EMI_SDMR_OFFSET + h'04)
EMI_LTC0_LOW .equ (SH7770_EMI_BASE + EMI_LTC0_OFFSET + h'04)
EMI_LTAD0_LOW .equ (SH7770_EMI_BASE + EMI_LTAD0_OFFSET + h'04)
EMI_LTAM0_LOW .equ (SH7770_EMI_BASE + EMI_LTAM0_OFFSET + h'04)
EMI_LTC1_LOW .equ (SH7770_EMI_BASE + EMI_LTC1_OFFSET + h'04)
EMI_LTAD1_LOW .equ (SH7770_EMI_BASE + EMI_LTAD1_OFFSET + h'04)
EMI_LTAM1_LOW .equ (SH7770_EMI_BASE + EMI_LTAM1_OFFSET + h'04)
EMI_LTC2_LOW .equ (SH7770_EMI_BASE + EMI_LTC2_OFFSET + h'04)
EMI_LTAD2_LOW .equ (SH7770_EMI_BASE + EMI_LTAD2_OFFSET + h'04)
EMI_LTAM2_LOW .equ (SH7770_EMI_BASE + EMI_LTAM2_OFFSET + h'04)
EMI_LTC3_LOW .equ (SH7770_EMI_BASE + EMI_LTC3_OFFSET + h'04)
EMI_LTAD3_LOW .equ (SH7770_EMI_BASE + EMI_LTAD3_OFFSET + h'04)
EMI_LTAM3_LOW .equ (SH7770_EMI_BASE + EMI_LTAM3_OFFSET + h'04)
EMI_LTC4_LOW .equ (SH7770_EMI_BASE + EMI_LTC4_OFFSET + h'04)
EMI_LTAD4_LOW .equ (SH7770_EMI_BASE + EMI_LTAD4_OFFSET + h'04)
EMI_LTAM4_LOW .equ (SH7770_EMI_BASE + EMI_LTAM4_OFFSET + h'04)
EMI_LTC5_LOW .equ (SH7770_EMI_BASE + EMI_LTC5_OFFSET + h'04)
EMI_LTAD5_LOW .equ (SH7770_EMI_BASE + EMI_LTAD5_OFFSET + h'04)
EMI_LTAM5_LOW .equ (SH7770_EMI_BASE + EMI_LTAM5_OFFSET + h'04)
EMI_LTC6_LOW .equ (SH7770_EMI_BASE + EMI_LTC6_OFFSET + h'04)
EMI_LTAD6_LOW .equ (SH7770_EMI_BASE + EMI_LTAD6_OFFSET + h'04)
EMI_LTAM6_LOW .equ (SH7770_EMI_BASE + EMI_LTAM6_OFFSET + h'04)
EMI_LTC7_LOW .equ (SH7770_EMI_BASE + EMI_LTC7_OFFSET + h'04)
EMI_LTAD7_LOW .equ (SH7770_EMI_BASE + EMI_LTAD7_OFFSET + h'04)
EMI_LTAM7_LOW .equ (SH7770_EMI_BASE + EMI_LTAM7_OFFSET + h'04)
EMI_DBK_LOW .equ (SH7770_EMI_BASE + EMI_DBK_OFFSET + h'04)
;
; MIM
;
EMI_MIM_H_BOMODE_OPEN .equ h'00000000
EMI_MIM_H_BOMODE_CLOSE .equ h'00004000
EMI_MIM_H_PCKE_DISABLE .equ h'00000000
EMI_MIM_H_PCKE_ENABLE .equ h'00001000
EMI_MIM_H_SELFS_NOSELF .equ h'00000000
EMI_MIM_H_SELFS_SELF .equ h'00000004
EMI_MIM_H_RMODE_AUTOREF .equ h'00000000
EMI_MIM_H_RMODE_SELFREF .equ h'00000002
EMI_MIM_L_DRI .equ h'030d0000
EMI_MIM_L_DRE_DISABLE .equ h'00000000
EMI_MIM_L_DRE_ENABLE .equ h'00000200
EMI_MIM_L_ENDIAN_LITTLE .equ h'00000000
EMI_MIM_L_ENDIAN_BIG .equ h'00000100
EMI_MIM_L_BW_32BIT .equ h'00000040
EMI_MIM_L_BW_64BIT .equ h'00000080
EMI_MIM_L_DCE_DISABLE .equ h'00000000
EMI_MIM_L_DCE_ENABLE .equ h'00000001
EMI_MIM_SETUP1 .equ ( EMI_MIM_L_DRI |
+ EMI_MIM_L_DRE_DISABLE |
+ EMI_MIM_L_ENDIAN_LITTLE |
+ EMI_MIM_L_BW_64BIT |
+ EMI_MIM_L_DCE_ENABLE )
EMI_MIM_SETUP2 .equ ( EMI_MIM_L_DRI |
+ EMI_MIM_L_DRE_ENABLE |
+ EMI_MIM_L_ENDIAN_LITTLE |
+ EMI_MIM_L_BW_64BIT |
+ EMI_MIM_L_DCE_ENABLE )
;
; SCR
;
EMI_SCR_NORMAL .equ h'00000000
EMI_SCR_NOP .equ h'00000001
EMI_SCR_PALL .equ h'00000002
EMI_SCR_CKE .equ h'00000003
EMI_SCR_CBR .equ h'00000004
;
; STR
;
EMI_STR_WR_3 .equ h'00000000
EMI_STR_WR_4 .equ h'00040000
EMI_STR_WR_5 .equ h'00080000
EMI_STR_WR_6 .equ h'000C0000
EMI_STR_RW_3 .equ h'00000000
EMI_STR_RW_4 .equ h'00010000
EMI_STR_RW_5 .equ h'00020000
EMI_STR_RW_6 .equ h'00030000
EMI_STR_SRFC_6 .equ h'00000000
EMI_STR_SRFC_7 .equ h'00002000
EMI_STR_SRFC_8 .equ h'00004000
EMI_STR_SRFC_9 .equ h'00006000
EMI_STR_SRFC_12 .equ h'00008000
EMI_STR_SRFC_13 .equ h'0000A000
EMI_STR_SRFC_14 .equ h'0000C000
EMI_STR_SRFC_15 .equ h'0000E000
EMI_STR_SWR_2 .equ h'00000000
EMI_STR_SWR_3 .equ h'00001000
EMI_STR_SRRD_2 .equ h'00000000
EMI_STR_SRRD_3 .equ h'00000800
EMI_STR_SRAS_4 .equ h'00000000
EMI_STR_SRAS_5 .equ h'00000100
EMI_STR_SRAS_6 .equ h'00000200
EMI_STR_SRAS_7 .equ h'00000300
EMI_STR_SRAS_8 .equ h'00000400
EMI_STR_SRAS_9 .equ h'00000500
EMI_STR_SRC_6 .equ h'00000000
EMI_STR_SRC_7 .equ h'00000020
EMI_STR_SRC_8 .equ h'00000040
EMI_STR_SRC_9 .equ h'00000060
EMI_STR_SCL_2 .equ h'00000000
EMI_STR_SCL_25 .equ h'00000004
EMI_STR_SRCD_2 .equ h'00000000
EMI_STR_SRCD_3 .equ h'00000002
EMI_STR_SRP_2 .equ h'00000000
EMI_STR_SRP_3 .equ h'00000001
EMI_STR_DEFAULT .equ ( EMI_STR_SRP_2 |
+ EMI_STR_SRCD_2 |
+ EMI_STR_SCL_2 |
+ EMI_STR_SRC_7 |
+ EMI_STR_SRAS_4 |
+ EMI_STR_SRRD_2 |
+ EMI_STR_SWR_2 |
+ EMI_STR_SRFC_8 |
+ EMI_STR_RW_3 |
+ EMI_STR_WR_3 )
EMI_SDRA_SPLIT_12x9 .equ h'00000100
EMI_SDRA_SPLIT_13x9 .equ h'00000300
EMI_SDRA_SPLIT_13x10 .equ h'00000400
EMI_SDRA_SPLIT_14x10 .equ h'00000600
EMI_SDMR_MA0_HIGH .equ h'FEC00008
EMI_SDMR_MA1_HIGH .equ h'FEC00010
EMI_SDMR_MA2_HIGH .equ h'FEC00020
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