?? sh7770.inc
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EMI_SDMR_MA3_HIGH .equ h'FEC00040
EMI_SDMR_MA4_HIGH .equ h'FEC00080
EMI_SDMR_MA5_HIGH .equ h'FEC00100
EMI_SDMR_MA6_HIGH .equ h'FEC00200
EMI_SDMR_MA7_HIGH .equ h'FEC00400
EMI_SDMR_MA8_HIGH .equ h'FEC00800
EMI_SDMR_MA9_HIGH .equ h'FEC01000
EMI_SDMR_MA10_HIGH .equ h'FEC08000
EMI_SDMR_MA11_HIGH .equ h'FEC10000
EMI_SDMR_MA12_HIGH .equ h'FEC20000
EMI_SDMR_MA13_HIGH .equ h'FEC40000
EMI_SDMR_BA0_HIGH .equ h'FEC02000
EMI_SDMR_BA1_HIGH .equ h'FEC04000
;
; for Bus bridge Internal Register
;
SH7770_VCRSYS_OFFSET .equ h'00000000
SH7770_BSC_OFFSET .equ h'00000200
SH7770_DMAC_OFFSET .equ h'00001000
;
; for Bus bridge Internal IP
;
SH7770_YUV_OFFSET .equ h'00100000
SH7770_VIN_OFFSET .equ h'00101000
SH7770_ATAPI_OFFSET .equ h'00102000
SH7770_USBHOST_OFFSET .equ h'00103000
SH7770_USBFUNC_OFFSET .equ h'00104000
SH7770_SPDIF_OFFSET .equ h'00105000
SH7770_HAC_OFFSET .equ h'00106000
SH7770_I2C_OFFSET .equ h'00107000
SH7770_HCAN_OFFSET .equ h'00108000
SH7770_SSI0_OFFSET .equ h'00110000
SH7770_SSI1_OFFSET .equ h'00111000
SH7770_SSI2_OFFSET .equ h'00112000
SH7770_SSI3_OFFSET .equ h'00113000
SH7770_SRC_OFFSET .equ h'00122000
SH7770_SCIF0_OFFSET .equ h'00123000
SH7770_SCIF1_OFFSET .equ h'00124000
SH7770_SCIF2_OFFSET .equ h'00125000
SH7770_SCIF3_OFFSET .equ h'00126000
SH7770_SCIF4_OFFSET .equ h'00127000
SH7770_SCIF5_OFFSET .equ h'00128000
SH7770_SCIF6_OFFSET .equ h'00129000
SH7770_SCIF7_OFFSET .equ h'0012A000
SH7770_SCIF8_OFFSET .equ h'0012B000
SH7770_SCIF9_OFFSET .equ h'0012C000
SH7770_HSPI0_OFFSET .equ h'0012F000
SH7770_HSPI1_OFFSET .equ h'00130000
SH7770_PWM_OFFSET .equ h'00131000
SH7770_REMOCON_OFFSET .equ h'00137000
SH7770_MOST_OFFSET .equ h'0013A000
SH7770_ADC_OFFSET .equ h'0013C000
SH7770_GPS_OFFSET .equ h'0013D000
SH7770_GPIO_OFFSET .equ h'0013E000
SH7770_INTC_USERIMASK_OFFSET .equ h'00150000
SH7770_CPG_OFFSET .equ h'00400000
SH7770_RESET_OFFSET .equ h'00440000
SH7770_RTC_OFFSET .equ h'00480000
SH7770_INTC_OFFSET .equ h'00500000
SH7770_TMU012_OFFSET .equ h'00580000
SH7770_TMU345_OFFSET .equ h'00581000
SH7770_TMU678_OFFSET .equ h'00582000
SH7770_INTC2_OFFSET .equ h'00600000
SH7770_2DG_OFFSET .equ h'00680000
SH7770_DU_OFFSET .equ h'00700000
;
; for Bus bridge
; Definitions for VCRSYS
;
VCRSYS_REGBASE .equ (SH7770_BUSBRIDGE_BASE+SH7770_VCRSYS_OFFSET)
VCRSYS_REGSIZE .equ h'00000200
VCRSYS_BBGVCR0_OFFSET .equ h'00000000
VCRSYS_BBGVCR1_OFFSET .equ h'00000004
VCRSYS_BBGVCEAR_OFFSET .equ h'00000008
VCRSYS_CLKCR_OFFSET .equ h'0000000C
VCRSYS_PMMR_OFFSET .equ h'00000010
VCRSYS_PMSR1_OFFSET .equ h'00000014
VCRSYS_PMSR2_OFFSET .equ h'00000018
VCRSYS_PMSR3_OFFSET .equ h'0000001C
VCRSYS_PMSR4_OFFSET .equ h'00000020
VCRSYS_PMSRG_OFFSET .equ h'00000024
VCRSYS_DBGSTR_OFFSET .equ h'00000028
VCRSYS_DBR2_OFFSET .equ h'00000040
VCRSYS_DRR2_OFFSET .equ h'00000044
VCRSYS_DAR2_OFFSET .equ h'00000048
VCRSYS_DAMR2_OFFSET .equ h'0000004C
VCRSYS_DCBR10_OFFSET .equ h'00000050
VCRSYS_DBR3_OFFSET .equ h'00000060
VCRSYS_DRR3_OFFSET .equ h'00000064
VCRSYS_DAR3_OFFSET .equ h'00000068
VCRSYS_DAMR3_OFFSET .equ h'0000006C
VCRSYS_DCBR11_OFFSET .equ h'00000070
VCRSYS_ECPUCR_OFFSET .equ h'00000100
VCRSYS_ECPUMR_OFFSET .equ h'00000104
VCRSYS_BBGIR_OFFSET .equ h'00000108
VCRSYS_ECPUIR_OFFSET .equ h'0000010C
VCRSYS_ECPUER_OFFSET .equ h'00000110
VCRSYS_ECPUEIR_OFFSET .equ h'00000114
VCRSYS_BBGVCR0 .equ (VCRSYS_REGBASE + VCRSYS_BBGVCR0_OFFSET)
VCRSYS_BBGVCR1 .equ (VCRSYS_REGBASE + VCRSYS_BBGVCR1_OFFSET)
VCRSYS_BBGVCEAR .equ (VCRSYS_REGBASE + VCRSYS_BBGVCEAR_OFFSET)
VCRSYS_CLKCR .equ (VCRSYS_REGBASE + VCRSYS_CLKCR_OFFSET)
VCRSYS_PMMR .equ (VCRSYS_REGBASE + VCRSYS_PMMR_OFFSET)
VCRSYS_PMSR1 .equ (VCRSYS_REGBASE + VCRSYS_PMSR1_OFFSET)
VCRSYS_PMSR2 .equ (VCRSYS_REGBASE + VCRSYS_PMSR2_OFFSET)
VCRSYS_PMSR3 .equ (VCRSYS_REGBASE + VCRSYS_PMSR3_OFFSET)
VCRSYS_PMSR4 .equ (VCRSYS_REGBASE + VCRSYS_PMSR4_OFFSET)
VCRSYS_PMSRG .equ (VCRSYS_REGBASE + VCRSYS_PMSRG_OFFSET)
VCRSYS_DGBSTR .equ (VCRSYS_REGBASE + VCRSYS_DBGSTR_OFFSET)
VCRSYS_DBR2 .equ (VCRSYS_REGBASE + VCRSYS_DBR2_OFFSET)
VCRSYS_DRR2 .equ (VCRSYS_REGBASE + VCRSYS_DRR2_OFFSET)
VCRSYS_DAR2 .equ (VCRSYS_REGBASE + VCRSYS_DAR2_OFFSET)
VCRSYS_DAMR2 .equ (VCRSYS_REGBASE + VCRSYS_DAMR2_OFFSET)
VCRSYS_DCBR10 .equ (VCRSYS_REGBASE + VCRSYS_DCBR10_OFFSET)
VCRSYS_DBR3 .equ (VCRSYS_REGBASE + VCRSYS_DBR3_OFFSET)
VCRSYS_DRR3 .equ (VCRSYS_REGBASE + VCRSYS_DRR3_OFFSET)
VCRSYS_DAR3 .equ (VCRSYS_REGBASE + VCRSYS_DAMR3_OFFSET)
VCRSYS_DAMR3 .equ (VCRSYS_REGBASE + VCRSYS_DAMR3_OFFSET)
VCRSYS_DCBR11 .equ (VCRSYS_REGBASE + VCRSYS_DCBR11_OFFSET)
VCRSYS_ECPUCR .equ (VCRSYS_REGBASE + VCRSYS_ECPUCR_OFFSET)
VCRSYS_ECPUMR .equ (VCRSYS_REGBASE + VCRSYS_ECPUMR_OFFSET)
VCRSYS_BBGIR .equ (VCRSYS_REGBASE + VCRSYS_BBGIR_OFFSET)
VCRSYS_ECPUIR .equ (VCRSYS_REGBASE + VCRSYS_ECPUIR_OFFSET)
VCRSYS_ECPUER .equ (VCRSYS_REGBASE + VCRSYS_ECPUER_OFFSET)
VCRSYS_ECPUEIR .equ (VCRSYS_REGBASE + VCRSYS_ECPUEIR_OFFSET)
; Definitions for VCRSYS BBGVCR1
VCRSYS_BBGVCR1_MERR_FLAGS .equ h'0000FF00 ; Display MERR FLAGS
VCRSYS_BBGVCR1_MERR_WT_CNL .equ h'00000800 ; Display MERR FLAGS(WT_CNL)
VCRSYS_BBGVCR1_MERR_BAD_BE .equ h'00000400 ; Display MERR FLAGS(BAD_BE)
VCRSYS_BBGVCR1_MERR_BAD_SIZE .equ h'00000200 ; Display MERR FLAGS(BAD_SIZE)
VCRSYS_BBGVCR1_MERR_BAD_TRS .equ h'00000100 ; Display MERR FLAGS(BAD_TRS)
VCRSYS_BBGVCR1_PERR_FLAGS .equ h'0000002F ; Display PERR_FLAGS
VCRSYS_BBGVCR1_PERR_BAD_OPC .equ h'00000020 ; Display PERR_FLAGS (Received Not-support opcode)
VCRSYS_BBGVCR1_PERR_UNSOL_RESP .equ h'00000008 ; Display PERR_FLAGS (Received Uncorresponding response packet)
VCRSYS_BBGVCR1_PERR_BAD_ADDR .equ h'00000004 ; Display PERR_FLAGS (Received Undefined Area access)
VCRSYS_BBGVCR1_PERR_ERR_SNT .equ h'00000002 ; Display PERR_FLAGS (Sent Error Response)
VCRSYS_BBGVCR1_PERR_ERR_RCV .equ h'00000001 ; Display PERR_FLAGS (Received Error Response)
; Definitions for VCRSYS CLKCR
VCRSYS_CLKCR_3DCLKSEL_OFF .equ h'00000080 ; For 3D internal Clock 100MHz for 2ndCut
VCRSYS_CLKCR_3DCLKSEL_ON .equ h'00000000 ; For internal 3D Clock 50MHz for 2ndCut
VCRSYS_CLKCR_GPSCLKSTP_OFF .equ h'00000040 ; For GPS Clock OFF
VCRSYS_CLKCR_GPSCLKSTP_ON .equ h'00000000 ; For GPS Clock ON
VCRSYS_CLKCR_CLKSTP_OFF .equ h'00000020 ; For Reserved Module Clock OFF
VCRSYS_CLKCR_CLKSTP_ON .equ h'00000000 ; For Reserved Module Clock ON
VCRSYS_CLKCR_U1CLKSTPl_OFF .equ h'00000010 ; For USB1.1 Clock OFF
VCRSYS_CLKCR_U1CLKSTPl_ON .equ h'00000000 ; For USB1.1 Clock ON
VCRSYS_CLKCR_VINCLKCR_OFF .equ h'00000008 ; For VIN Clock OFF
VCRSYS_CLKCR_VINCLKCR_ON .equ h'00000000 ; For VIN Clock ON
VCRSYS_CLKCR_DUCLKSTP_OFF .equ h'00000004 ; For DU Clock OFF
VCRSYS_CLKCR_DUCLKSTP_ON .equ h'00000000 ; For DU Clock ON
VCRSYS_CLKCR_3DCLKSTP_OFF .equ h'00000002 ; For 3D Clock OFF
VCRSYS_CLKCR_3DCLKSTP_ON .equ h'00000000 ; For 3D Clock ON
VCRSYS_CLKCR_2DCLKSTP_OFF .equ h'00000001 ; For 2D Clock OFF
VCRSYS_CLKCR_2DCLKSTP_ON .equ h'00000000 ; For 2D Clock ON
; Definitions for VCRSYS PMSR1
VCRSYS_PMSR1_IR5_IRQ5 .equ h'00000000 ; IRQ5
VCRSYS_PMSR1_IR5_EX_CS7 .equ h'10000000 ; EX_CS7 (Default)
VCRSYS_PMSR1_IR4_IRQ4 .equ h'00000000 ; IRQ4
VCRSYS_PMSR1_IR4_EX_CS6 .equ h'08000000 ; EX_CS6 (Default)
VCRSYS_PMSR1_IR3_IRQ3 .equ h'00000000 ; IRQ3
VCRSYS_PMSR1_IR3_EX_CS5 .equ h'04000000 ; EX_CS5 (Default)
VCRSYS_PMSR1_IR2_IRQ2 .equ h'00000000 ; IRQ2
VCRSYS_PMSR1_IR2_EX_WAIT2 .equ h'02000000 ; EX_WAIT2 (Default)
VCRSYS_PMSR1_IR1_IRQ1 .equ h'00000000 ; IRQ1
VCRSYS_PMSR1_IR1_EX_WAIT1 .equ h'01000000 ; EX_WAIT1 (Default)
VCRSYS_PMSR1_EXA_EXBUS .equ h'00000000 ; EXBUS25-11(Default)
VCRSYS_PMSR1_EXA_GPIO .equ h'00040000 ; GPIO
VCRSYS_PMSR1_ATAPI_ATAPI .equ h'00000000 ; ATAPI
VCRSYS_PMSR1_ATAPI_GPIO .equ h'00010000 ; GPIO (Default)
VCRSYS_PMSR1_EXD31_GPIO .equ h'00000000 ; GPIO
VCRSYS_PMSR1_EXD31_EXBUS .equ h'00004000 ; EXBUS (Default)
VCRSYS_PMSR1_EXD15_EXBUS .equ h'00000000 ; EXBUS (Default)
VCRSYS_PMSR1_EXD15_GPIO .equ h'00002000 ; GPIO
VCRSYS_PMSR1_EXCP_EXCS .equ h'00000000 ; EX_CS4 (Default)
VCRSYS_PMSR1_EXCS1_EXCS .equ h'00000000 ; EX_CS1 (Default)
VCRSYS_PMSR1_EXCS1_GPIO .equ h'00000100 ; GPIO
VCRSYS_PMSR1_EXCS0_EXCS .equ h'00000000 ; EX_CS0 (Default)
VCRSYS_PMSR1_EXCS0_GPIO .equ h'00000080 ; GPIO
VCRSYS_PMSR1_CS1_CS .equ h'00000000 ; CS1 (Default)
VCRSYS_PMSR1_CS1_GPIO .equ h'00000040 ; GPIO
VCRSYS_PMSR1_DREQ1_DREQ .equ h'00000000 ; DREQ1 (Default)
VCRSYS_PMSR1_DREQ1_GPIO .equ h'00000020 ; GPIO
VCRSYS_PMSR1_DREQ0_DREQ .equ h'00000000 ; DREQ0 (Default)
VCRSYS_PMSR1_DREQ0_GPIO .equ h'00000010 ; GPIO
VCRSYS_PMSR1_DACK1_DACK .equ h'00000000 ; DACK1 (Default)
VCRSYS_PMSR1_DACK1_GPIO .equ h'00000008 ; GPIO
VCRSYS_PMSR1_DACK0_DACK .equ h'00000000 ; DACK0 (Default)
VCRSYS_PMSR1_DACK0_GIPO .equ h'00000004 ; GPIO
VCRSYS_PMSR1_DRACK0_DRACK .equ h'00000000 ; DRACK0 (Default)
VCRSYS_PMSR1_DRACK0_GPIO .equ h'00000002 ; GPIO
; Definitions for VCRSYS PMSR2
VCRSYS_PMSR2_SCICK_SCIF .equ h'00000000 ; SCIF CLK
VCRSYS_PMSR2_SCICK_GPIO .equ h'80000000 ; GPIO
VCRSYS_PMSR2_SCIF9_GPIO .equ h'00000000 ; GPIO
VCRSYS_PMSR2_SCIF9_SCIF .equ h'02000000 ; SCIF9
VCRSYS_PMSR2_SCIF7_SCIF .equ h'00000000 ; SCIF7
VCRSYS_PMSR2_SCIF7_HSPI .equ h'00800000 ; HSPI1
VCRSYS_PMSR2_SCIF7_SCK .equ h'01800000 ; SCK
VCRSYS_PMSR2_SCIF6_RX .equ h'00000000 ; RX6
VCRSYS_PMSR2_SCIF6_I2C .equ h'00400000 ; I2C_SDA
VCRSYS_PMSR2_SCIF4_HSPI .equ h'00000000 ; HSPI0
VCRSYS_PMSR2_SCIF4_SCIF .equ h'00100000 ; SCIF4,5
VCRSYS_PMSR2_SCIF3_GPIO .equ h'00000000 ; GPIO
VCRSYS_PMSR2_SCIF3_SCIF .equ h'00080000 ; SCIF3
VCRSYS_PMSR2_SCIF2_GPIO .equ h'00000000 ; GPIO
VCRSYS_PMSR2_SCIF2_SCIF .equ h'00040000 ; SCIF2
VCRSYS_PMSR2_SCIF0_GPIO .equ h'00000000 ; GPIO
VCRSYS_PMSR2_SCIF0_SCIF0_GPIO .equ h'00010000 ; SCIF0(Tx,Rx), GPIO
VCRSYS_PMSR2_SCIF0_SCIF0 .equ h'00020000 ; SCIF0(Tx,Rx,RTS,CTS)
VCRSYS_PMSR2_SCIF0_SCIF0_1 .equ h'00030000 ; SCIF0(Tx,Rx), SCIF1(Tx,Rx)
VCRSYS_PMSR2_ADOCK_AUDIO .equ h'00000000 ; AUDIO_CLK
VCRSYS_PMSR2_ADOCK_GPIO .equ h'00008000 ; GPIO
VCRSYS_PMSR2_HARES_SSI .equ h'00000000 ; SSI_WS1
VCRSYS_PMSR2_HARES_HAC .equ h'00004000 ; HAC_RES
VCRSYS_PMSR2_SSI23_SSI .equ h'00000000 ; SSI2,3
VCRSYS_PMSR2_SSI23_HAC .equ h'00001000 ; HAC
VCRSYS_PMSR2_SSI1_SSI .equ h'00000000 ; SSI1
VCRSYS_PMSR2_SSI1_GPIO .equ h'00000800 ; HAC
VCRSYS_PMSR2_SSI0_SSI .equ h'00000000 ; SSI0
VCRSYS_PMSR2_SSI0_GPIO .equ h'00000400 ; GPIO
VCRSYS_PMSR2_SPDIF1_GPIO .equ h'00000000 ; GPIO
VCRSYS_PMSR2_SPDIF1_SPDIF .equ h'00000100 ; SPDIF
VCRSYS_PMSR2_SPDIF1_PIO .equ h'00000200 ; PIO
VCRSYS_PMSR2_SPDIF0_GPIO .equ h'00000000 ; GPIO
VCRSYS_PMSR2_SPDIF0_SPDIF .equ h'00000040 ; SPDIF
VCRSYS_PMSR2_SPDIF0_PIO .equ h'00000080 ; PIO
VCRSYS_PMSR2_CDE_CDE .equ h'00000000 ; CDE
VCRSYS_PMSR2_CDE_GPIO .equ h'00000004 ; GPIO
VCRSYS_PMSR2_ODDF_ODDF .equ h'00000000 ; ODDF
VCRSYS_PMSR2_ODDF_GPIO .equ h'00000002 ; GPIO
; Definitions for VCRSYS PMSR3
VCRSYS_PMSR3_REMC_IRREC .equ h'00000000 ; IRREC
VCRSYS_PMSR3_REMC_GPIO .equ h'00000040 ; GPIO
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