?? sh7770.inc
字號:
VCRSYS_DCBR_DUC_STOP .equ h'00000000 ; PPC Curcuit STOP
VCRSYS_DCBR_DUC_COUNT .equ h'00000008 ; PPC Curcuit COUNT
VCRSYS_DCBR_CMDS_TRIGER .equ h'00000000 ; Count mode : Triger
VCRSYS_DCBR_CMDS_DIRECT .equ h'00000000 ; Count mode : Direct
VCRSYS_DCBR_PPCE_DISABLE .equ h'00000000 ; PPC Disable
VCRSYS_DCBR_PPCE_ENABLE .equ h'00000001 ; PPC Enable
; Definitions for VCRSYS ECPUCR
VCRSYS_ECPUCR_ECPENB .equ h'00000002 ; External CPU Connect 0:Disable 1:Enable
VCRSYS_ECPUCR_ECPSEL .equ h'00000001 ; External CPU Select 0:SH7751 1:SH7750
; Definitions for VCRSYS ECPUMR
VCRSYS_ECPUIR_ECPINT .equ h'00000001 ; Notice of Interrupts to INTC 0:Disable 1:Enable
;
; for Bus bridge
; Definitions for BSC
;
SH7770_BSC_REGBASE .equ (SH7770_BUSBRIDGE_BASE+SH7770_BSC_OFFSET)
SH7770_BSC_REGSIZE .equ h'00000500
BSC_CS0CTRL_OFFSET .equ h'00000000
BSC_CS1CTRL_OFFSET .equ h'00000004
BSC_ECS0CTRL_OFFSET .equ h'00000008
BSC_ECS1CTRL_OFFSET .equ h'0000000C
BSC_ECS2CTRL_OFFSET .equ h'00000010
BSC_ECS3CTRL_OFFSET .equ h'00000014
BSC_ECS4CTRL_OFFSET .equ h'00000018
BSC_ECS5CTRL_OFFSET .equ h'0000001C
BSC_ECS6CTRL_OFFSET .equ h'00000020
BSC_ECS7CTRL_OFFSET .equ h'00000024
BSC_CSWCR0_OFFSET .equ h'00000030
BSC_CSWCR1_OFFSET .equ h'00000034
BSC_ECSWCR0_OFFSET .equ h'00000038
BSC_ECSWCR1_OFFSET .equ h'0000003C
BSC_ECSWCR2_OFFSET .equ h'00000040
BSC_ECSWCR3_OFFSET .equ h'00000044
BSC_ECSWCR4_OFFSET .equ h'00000048
BSC_ECSWCR5_OFFSET .equ h'0000004C
BSC_ECSWCR6_OFFSET .equ h'00000050
BSC_ECSWCR7_OFFSET .equ h'00000054
BSC_EXDMWCR0_OFFSET .equ h'00000058
BSC_EXDMWCR1_OFFSET .equ h'0000005C
BSC_EXDMWCR2_OFFSET .equ h'00000060
BSC_EXDMWCR3_OFFSET .equ h'00000064
BSC_EXDMWCR4_OFFSET .equ h'00000068
BSC_CSPWCR0_OFFSET .equ h'00000070
BSC_CSPWCR1_OFFSET .equ h'00000074
BSC_ECSPWCR0_OFFSET .equ h'00000078
BSC_ECSPWCR1_OFFSET .equ h'0000007C
BSC_ECSPWCR2_OFFSET .equ h'00000080
BSC_ECSPWCR3_OFFSET .equ h'00000084
BSC_ECSPWCR4_OFFSET .equ h'00000088
BSC_ECSPWCR5_OFFSET .equ h'0000008C
BSC_ECSPWCR6_OFFSET .equ h'00000090
BSC_ECSPWCR7_OFFSET .equ h'00000094
BSC_EXWTSYNC_OFFSET .equ h'00000098
BSC_CS0BSTCTL_OFFSET .equ h'000000A0
BSC_CS0BTPH_OFFSET .equ h'000000A4
BSC_CS1GDST_OFFSET .equ h'000000B0
BSC_ECS0GDST_OFFSET .equ h'000000B4
BSC_ECS1GDST_OFFSET .equ h'000000B8
BSC_ECS2GDST_OFFSET .equ h'000000BC
BSC_ECS3GDST_OFFSET .equ h'000000C0
BSC_ECS4GDST_OFFSET .equ h'000000C4
BSC_ECS5GDST_OFFSET .equ h'000000C8
BSC_ECS6GDST_OFFSET .equ h'000000CC
BSC_ECS7GDST_OFFSET .equ h'000000D0
BSC_EXDMASET0_OFFSET .equ h'000000E0
BSC_EXDMASET1_OFFSET .equ h'000000E4
BSC_EXDMASET2_OFFSET .equ h'000000E8
BSC_EXDMASET3_OFFSET .equ h'000000EC
BSC_EXDMASET4_OFFSET .equ h'000000F0
BSC_EXDMCR0_OFFSET .equ h'000000F4
BSC_EXDMCR1_OFFSET .equ h'000000F8
BSC_EXDMCR2_OFFSET .equ h'000000FC
BSC_EXDMCR3_OFFSET .equ h'00000100
BSC_EXDMCR4_OFFSET .equ h'00000104
BSC_BCINTSR_OFFSET .equ h'00000120
BSC_BCINTCR_OFFSET .equ h'00000124
BSC_BCINTMR_OFFSET .equ h'00000128
BSC_EXBATLV_OFFSET .equ h'00000130
BSC_EXPIN_OFFSET .equ h'00000200
BSC_EXPOUT_OFFSET .equ h'00000204
BSC_CS0CTRL .equ (SH7770_BSC_REGBASE + BSC_CS0CTRL_OFFSET)
BSC_CS1CTRL .equ (SH7770_BSC_REGBASE + BSC_CS1CTRL_OFFSET)
BSC_ECS0CTRL .equ (SH7770_BSC_REGBASE + BSC_ECS0CTRL_OFFSET)
BSC_ECS1CTRL .equ (SH7770_BSC_REGBASE + BSC_ECS1CTRL_OFFSET)
BSC_ECS2CTRL .equ (SH7770_BSC_REGBASE + BSC_ECS2CTRL_OFFSET)
BSC_ECS3CTRL .equ (SH7770_BSC_REGBASE + BSC_ECS3CTRL_OFFSET)
BSC_ECS4CTRL .equ (SH7770_BSC_REGBASE + BSC_ECS4CTRL_OFFSET)
BSC_ECS5CTRL .equ (SH7770_BSC_REGBASE + BSC_ECS5CTRL_OFFSET)
BSC_ECS6CTRL .equ (SH7770_BSC_REGBASE + BSC_ECS6CTRL_OFFSET)
BSC_ECS7CTRL .equ (SH7770_BSC_REGBASE + BSC_ECS7CTRL_OFFSET)
BSC_CSWCR0 .equ (SH7770_BSC_REGBASE + BSC_CSWCR0_OFFSET)
BSC_CSWCR1 .equ (SH7770_BSC_REGBASE + BSC_CSWCR1_OFFSET)
BSC_ECSWCR0 .equ (SH7770_BSC_REGBASE + BSC_ECSWCR0_OFFSET)
BSC_ECSWCR1 .equ (SH7770_BSC_REGBASE + BSC_ECSWCR1_OFFSET)
BSC_ECSWCR2 .equ (SH7770_BSC_REGBASE + BSC_ECSWCR2_OFFSET)
BSC_ECSWCR3 .equ (SH7770_BSC_REGBASE + BSC_ECSWCR3_OFFSET)
BSC_ECSWCR4 .equ (SH7770_BSC_REGBASE + BSC_ECSWCR4_OFFSET)
BSC_ECSWCR5 .equ (SH7770_BSC_REGBASE + BSC_ECSWCR5_OFFSET)
BSC_ECSWCR6 .equ (SH7770_BSC_REGBASE + BSC_ECSWCR6_OFFSET)
BSC_ECSWCR7 .equ (SH7770_BSC_REGBASE + BSC_ECSWCR7_OFFSET)
BSC_EXDMWCR0 .equ (SH7770_BSC_REGBASE + BSC_EXDMWCR0_OFFSET)
BSC_EXDMWCR1 .equ (SH7770_BSC_REGBASE + BSC_EXDMWCR1_OFFSET)
BSC_EXDMWCR2 .equ (SH7770_BSC_REGBASE + BSC_EXDMWCR2_OFFSET)
BSC_EXDMWCR3 .equ (SH7770_BSC_REGBASE + BSC_EXDMWCR3_OFFSET)
BSC_EXDMWCR4 .equ (SH7770_BSC_REGBASE + BSC_EXDMWCR4_OFFSET)
BSC_CSPWCR0 .equ (SH7770_BSC_REGBASE + BSC_CSPWCR0_OFFSET)
BSC_CSPWCR1 .equ (SH7770_BSC_REGBASE + BSC_CSPWCR1_OFFSET)
BSC_ECSPWCR0 .equ (SH7770_BSC_REGBASE + BSC_ECSPWCR0_OFFSET)
BSC_ECSPWCR1 .equ (SH7770_BSC_REGBASE + BSC_ECSPWCR1_OFFSET)
BSC_ECSPWCR2 .equ (SH7770_BSC_REGBASE + BSC_ECSPWCR2_OFFSET)
BSC_ECSPWCR3 .equ (SH7770_BSC_REGBASE + BSC_ECSPWCR3_OFFSET)
BSC_ECSPWCR4 .equ (SH7770_BSC_REGBASE + BSC_ECSPWCR4_OFFSET)
BSC_ECSPWCR5 .equ (SH7770_BSC_REGBASE + BSC_ECSPWCR5_OFFSET)
BSC_ECSPWCR6 .equ (SH7770_BSC_REGBASE + BSC_ECSPWCR6_OFFSET)
BSC_ECSPWCR7 .equ (SH7770_BSC_REGBASE + BSC_ECSPWCR7_OFFSET)
BSC_EXWTSYNC .equ (SH7770_BSC_REGBASE + BSC_EXWTSYNC_OFFSET)
BSC_CS0BSTCTL .equ (SH7770_BSC_REGBASE + BSC_CS0BSTCTL_OFFSET)
BSC_CS0BTPH .equ (SH7770_BSC_REGBASE + BSC_CS0BTPH_OFFSET)
BSC_CS1GDST .equ (SH7770_BSC_REGBASE + BSC_CS1GDST_OFFSET)
BSC_ECS0GDST .equ (SH7770_BSC_REGBASE + BSC_ECS0GDST_OFFSET)
BSC_ECS1GDST .equ (SH7770_BSC_REGBASE + BSC_ECS1GDST_OFFSET)
BSC_ECS2GDST .equ (SH7770_BSC_REGBASE + BSC_ECS2GDST_OFFSET)
BSC_ECS3GDST .equ (SH7770_BSC_REGBASE + BSC_ECS3GDST_OFFSET)
BSC_ECS4GDST .equ (SH7770_BSC_REGBASE + BSC_ECS4GDST_OFFSET)
BSC_ECS5GDST .equ (SH7770_BSC_REGBASE + BSC_ECS5GDST_OFFSET)
BSC_ECS6GDST .equ (SH7770_BSC_REGBASE + BSC_ECS6GDST_OFFSET)
BSC_ECS7GDST .equ (SH7770_BSC_REGBASE + BSC_ECS7GDST_OFFSET)
BSC_EXDMASET0 .equ (SH7770_BSC_REGBASE + BSC_EXDMASET0_OFFSET)
BSC_EXDMASET1 .equ (SH7770_BSC_REGBASE + BSC_EXDMASET1_OFFSET)
BSC_EXDMASET2 .equ (SH7770_BSC_REGBASE + BSC_EXDMASET2_OFFSET)
BSC_EXDMASET3 .equ (SH7770_BSC_REGBASE + BSC_EXDMASET3_OFFSET)
BSC_EXDMASET4 .equ (SH7770_BSC_REGBASE + BSC_EXDMASET4_OFFSET)
BSC_EXDMCR0 .equ (SH7770_BSC_REGBASE + BSC_EXDMCR0_OFFSET)
BSC_EXDMCR1 .equ (SH7770_BSC_REGBASE + BSC_EXDMCR1_OFFSET)
BSC_EXDMCR2 .equ (SH7770_BSC_REGBASE + BSC_EXDMCR2_OFFSET)
BSC_EXDMCR3 .equ (SH7770_BSC_REGBASE + BSC_EXDMCR3_OFFSET)
BSC_EXDMCR4 .equ (SH7770_BSC_REGBASE + BSC_EXDMCR4_OFFSET)
BSC_BCINTSR .equ (SH7770_BSC_REGBASE + BSC_BCINTSR_OFFSET)
BSC_BCINTCR .equ (SH7770_BSC_REGBASE + BSC_BCINTCR_OFFSET)
BSC_BCINTMR .equ (SH7770_BSC_REGBASE + BSC_BCINTMR_OFFSET)
BSC_EXBATLV .equ (SH7770_BSC_REGBASE + BSC_EXBATLV_OFFSET)
BSC_EXPIN .equ (SH7770_BSC_REGBASE + BSC_EXPIN_OFFSET)
BSC_EXPOUT .equ (SH7770_BSC_REGBASE + BSC_EXPOUT_OFFSET)
; Definitions for BSC CS0,1CTRL
BSC_CSxCTRL_CSxSZ_16BIT .equ h'00000020 ; AREAx Bus Width (16bit)
BSC_CSxCTRL_CSxSZ_8BIT .equ h'00000010 ; AREAx Bus Width (8bit)
BSC_CSxCTRL_CSxSZ_32BIT .equ h'00000030 ; AREAx Bus Width (32bit)
BSC_CSxCTRL_CSxIF_STANDARD .equ h'00000000 ; AREAx Bus I/F (STANDARD/SRAM)
BSC_CSxCTRL_CSxIF_BURSTROM .equ h'00000001 ; AREAx Bus I/F (BurstROM)
; Definitions for BSC ECSxCTRL(x=0,1,2,3,4,5,6,7)
BSC_ECSxCTRL_ECSxCP_1M .equ h'00000100 ; External Areax Capacity (1MByte)
;BSC_ECSxCTRL_ECSxCP_7M .equ h'00000700 ; External Areax Capacity (7MByte)
BSC_ECSxCTRL_ECSxCP_8M .equ h'00000800 ; External Areax Capacity (8MByte)
BSC_ECSxCTRL_ECSxCP_64M .equ h'00004000 ; External Areax Capacity (64MByte)
BSC_ECSxCTRL_ECSxSZ_16BIT .equ h'00000020 ; External Areax Bus Width (16bit)
BSC_ECSxCTRL_ECSxSZ_8BIT .equ h'00000010 ; External Areax Bus Width ( 8bit)
BSC_ECSxCTRL_ECSxSZ_32BIT .equ h'00000030 ; External Areax Bus Width (32bit)
BSC_ECSxCTRL_ECSxIF_STANDARD .equ h'00000000 ; External Areax Bus I/F (STANDARD/SRAM)
BSC_ECSxCTRL_ECSxIF_ATA .equ h'00000002 ; External Area0 Bus I/F (ATA)
; Definitions for BSC CSWCR0/1, ECSWCRx, EXDMWCRy
BSC_CSWCR_WRSETUP_7 .equ h'07000000 ; write CS setup cycle
BSC_CSWCR_WRSETUP_6 .equ h'06000000
BSC_CSWCR_WRSETUP_5 .equ h'05000000
BSC_CSWCR_WRSETUP_4 .equ h'04000000
BSC_CSWCR_WRSETUP_3 .equ h'03000000
BSC_CSWCR_WRSETUP_2 .equ h'02000000
BSC_CSWCR_WRSETUP_1 .equ h'01000000
BSC_CSWCR_WRSETUP_0 .equ h'00000000
BSC_CSWCR_WRHOLD_7 .equ h'00700000 ; write CS hold cycle
BSC_CSWCR_WRHOLD_6 .equ h'00600000
BSC_CSWCR_WRHOLD_5 .equ h'00500000
BSC_CSWCR_WRHOLD_4 .equ h'00400000
BSC_CSWCR_WRHOLD_3 .equ h'00300000
BSC_CSWCR_WRHOLD_2 .equ h'00200000
BSC_CSWCR_WRHOLD_1 .equ h'00100000
BSC_CSWCR_WRHOLD_0 .equ h'00000000
BSC_CSWCR_WRPULSE_15 .equ h'000F0000 ; write pulse cycle
BSC_CSWCR_WRPULSE_14 .equ h'000E0000
BSC_CSWCR_WRPULSE_13 .equ h'000D0000
BSC_CSWCR_WRPULSE_12 .equ h'000C0000
BSC_CSWCR_WRPULSE_11 .equ h'000B0000
BSC_CSWCR_WRPULSE_10 .equ h'000A0000
BSC_CSWCR_WRPULSE_9 .equ h'00090000
BSC_CSWCR_WRPULSE_8 .equ h'00080000
BSC_CSWCR_WRPULSE_7 .equ h'00070000
BSC_CSWCR_WRPULSE_6 .equ h'00060000
BSC_CSWCR_WRPULSE_5 .equ h'00050000
BSC_CSWCR_WRPULSE_4 .equ h'00040000
BSC_CSWCR_WRPULSE_3 .equ h'00030000
BSC_CSWCR_WRPULSE_2 .equ h'00020000
BSC_CSWCR_WRPULSE_1 .equ h'00010000
BSC_CSWCR_RDSETUP_7 .equ h'00000700 ; read CS setup cycle
BSC_CSWCR_RDSETUP_6 .equ h'00000600
BSC_CSWCR_RDSETUP_5 .equ h'00000500
BSC_CSWCR_RDSETUP_4 .equ h'00000400
BSC_CSWCR_RDSETUP_3 .equ h'00000300
BSC_CSWCR_RDSETUP_2 .equ h'00000200
BSC_CSWCR_RDSETUP_1 .equ h'00000100
BSC_CSWCR_RDSETUP_0 .equ h'00000000
BSC_CSWCR_RDHOLD_7 .equ h'00000070 ; read CS hold cycle
BSC_CSWCR_RDHOLD_6 .equ h'00000060
BSC_CSWCR_RDHOLD_5 .equ h'00000050
BSC_CSWCR_RDHOLD_4 .equ h'00000040
BSC_CSWCR_RDHOLD_3 .equ h'00000030
BSC_CSWCR_RDHOLD_2 .equ h'00000020
BSC_CSWCR_RDHOLD_1 .equ h'00000010
BSC_CSWCR_RDHOLD_0 .equ h'00000000
BSC_CSWCR_RDPULSE_15 .equ h'0000000F ; read pulse cycle
BSC_CSWCR_RDPULSE_14 .equ h'0000000E
BSC_CSWCR_RDPULSE_13 .equ h'0000000D
BSC_CSWCR_RDPULSE_12 .equ h'0000000C
BSC_CSWCR_RDPULSE_11 .equ h'0000000B
BSC_CSWCR_RDPULSE_10 .equ h'0000000A
BSC_CSWCR_RDPULSE_9 .equ h'00000009
BSC_CSWCR_RDPULSE_8 .equ h'00000008
BSC_CSWCR_RDPULSE_7 .equ h'00000007
BSC_CSWCR_RDPULSE_6 .equ h'00000006
BSC_CSWCR_RDPULSE_5 .equ h'00000005
BSC_CSWCR_RDPULSE_4 .equ h'00000004
BSC_CSWCR_RDPULSE_3 .equ h'00000003
BSC_CSWCR_RDPULSE_2 .equ h'00000002
BSC_CSWCR_RDPULSE_1 .equ h'00000001
; Definitions for BSC CSPWCR0,1
BSC_CSPWCRx_V_DISABLE .equ h'00000000 ; AREAx External Wait Control Disable
BSC_CSPWCRx_V_ENABLE .equ h'00000020 ; AREAx External Wait Control Enable
BSC_CSPWCRx_RB_BUSY .equ h'00000000 ; AREAx READY/BUSY Logical Setting BUSY
BSC_CSPWCRx_RB_READY .equ h'00000010 ; AREAx READY/BUSY Logical Setting READY
BSC_CSPWCRx_WINV_NORMAL .equ h'00000000 ; AREAx Wait Signal Polarity Not Reverse
BSC_CSPWCRx_WINV_INV .equ h'00000008 ; AREAx Wait Signal Polarity Reverse
BSC_CSPWCRx_EXWT2_DISABLE .equ h'00000000 ; AREAx exwait2 Disable
BSC_CSPWCRx_EXWT2_ENABLE .equ h'00000004 ; AREAx exwait2 Enable
BSC_CSPWCRx_EXWT1_DISABLE .equ h'00000000 ; AREAx exwait1 Disable
BSC_CSPWCRx_EXWT1_ENABLE .equ h'00000002 ; AREAx exwait1 Enable
BSC_CSPWCRx_EXWT0_DISABLE .equ h'00000000 ; AREAx exwait0 Disable
BSC_CSPWCRx_EXWT0_ENABLE .equ h'00000001 ; AREAx exwait0 Enable
; Definitions for BSC ECSPWCR
BSC_ECSPWCRx_V_DISABLE .equ h'00000000 ; Ex AREA External Wait Control Disable
BSC_ECSPWCRx_V_ENABLE .equ h'00000020 ; Ex AREA External Wait Control Enable
BSC_ECSPWCRx_RB_BUSY .equ h'00000000 ; Ex AREA READY/BUSY Logical Setting BUSY
BSC_ECSPWCRx_RB_READY .equ h'00000010 ; Ex AREA READY/BUSY Logical Setting READY
BSC_ECSPWCRx_WINV_NORMAL .equ h'00000000 ; Ex AREA Wait Signal Polarity Not Reverse
BSC_ECSPWCRx_WINV_INV .equ h'00000008 ; Ex AREA Wait Signal Polarity Reverse
BSC_ECSPWCRx_EXWT2_DISABLE .equ h'00000000 ; Ex AREA exwait2 Disable
BSC_ECSPWCRx_EXWT2_ENABLE .equ h'00000004 ; Ex AREA exwait2 Enable
BSC_ECSPWCRx_EXWT1_DISABLE .equ h'00000000 ; Ex AREA exwait1 Disable
BSC_ECSPWCRx_EXWT1_ENABLE .equ h'00000002 ; Ex AREA exwait1 Enable
BSC_ECSPWCRx_EXWT0_DISABLE .equ h'00000000 ; Ex AREA exwait0 Disable
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