;
;  Copyright(C) Renesas Technology Corp. 2004. All rights reserved.
;
;  generic cache routines for ITS-DS7 Ver.0.8.0
;
;  FILE      : tlbclear.c
;  CREATED   : 2004.09.01
;  MODIFIED  : 
;  AUTHOR    : Renesas Technology Corp.
;  HARDWARE  : RENESAS ITS-DS7
;  HISTORY   : 
;              2004.09.01
;              - Created release code.
;                (based on ASPEN for WCE5.0)
;

;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
	.include "kxshx.h"
	.include "shx.inc"

    .align 4

; MMU control register
CCN_MMUCR_OFFSET		.equ	h'0010		; MMU control register offset
CCN_MMUCR				.equ	(CCN_REGBASE + CCN_MMUCR_OFFSET)	; MMU control register

; MMUCR values
TLB_ENABLE				.equ	h'0001		; enable TLB
TLB_FLUSH				.equ	h'0004		; flush TLB


;++
; Routine Description:
;    Flush and invalidate the entire unified TLB.
;
; Syntax:
;	void SH4ClearTLB(void);
;
; Arguments:
;	-- none --
;
; Return Value:
;	-- none --
;--
    LEAF_ENTRY _SH4ClearTLB

    mov		#CCN_MMUCR, r1				; r1 = MMUCR
    mov		#(TLB_ENABLE+TLB_FLUSH), r0	; r0 = TLB Flush and Enable
    rts
    mov.l	r0, @r1						; (delay slot) flush TLB

    .endf

	.end