//
//  Copyright(C) Renesas Technology Corp. 2003-2005. All rights reserved.
//
//  NK Kernel for ITS-DS7 Ver.1.0.0
//
//  FILE      : hac_isr.c
//  CREATED   : 2003.06.20
//  MODIFIED  : 2005.04.26
//  AUTHOR    : Renesas Technology Corp.
//  HARDWARE  : RENESAS ITS-DS7
//  HISTORY   : 
//              2003.06.20
//              - Created release code.
//              2004.09.01
//              - Created release code for WCE5.0.
//              2005.04.26
//              - Modified PCM data size from 20bit to 16bit Packed RX DMA.

#include <windows.h>
#include <platform.h>
#include <sh7770.h>
#include <oalintr.h>
#include <drv_glob.h>

#define HAC_ACR_OFFSET			0x0060

// HAC Control Register (ACR)
#define HAC_ACR_DMARX16			0x40000000		// 16 bit RX DMA Enable(30)
#define HAC_ACR_DMATX16			0x20000000		// 16 bit TX DMA Enable(29)
#define HAC_ACR_TX12_ATOMIC		0x04000000		// TX slots 1 and 2 atomic control(26)
#define HAC_ACR_RXDMAL_EN		0x01000000		// RX DMA Left Enable(24)
#define HAC_ACR_TXDMAL_EN		0x00800000		// TX DMA Left Enable(23)
#define HAC_ACR_RXDMAR_EN		0x00400000		// RX DMA Right Enable(22)
#define HAC_ACR_TXDMAR_EN		0x00200000		// TX DMA Right Enable(21)

#pragma optimize("", off)
//
// HAC ISR 0
// HAC module interrupts
//
int	hac_isr0(
	void
	)
{
#ifdef	DEBUG
	char string[8];
	static	int		ii = 0;
		// Output to LED (HAC Playing)
		string[0] = 'H';
		string[1] = 'A';
		string[2] = 'C';
		string[3] = '0';
		string[4] = '0' + (UCHAR)ii / 100;
		string[5] = '0' + (UCHAR)(ii %100) / 10;
		string[6] = '0' + (UCHAR)(ii % 10);
		string[7] = '\0';
		PrintLED(string);
		if( ++ii > 1000 )	ii = 0;
#endif
    return SYSINTR_NOP;
}

//
// HAC ISR 1
// DMA Transmitted (BusbridgeDMAC Ch0:HAC Playback)
//
int	hac_isr1(
	void
	)
{
    int		index, ch;
#ifdef	DEBUG
    char string[8];
    static	int		ii = 0;

		// Output to LED (HAC Playing)
		string[0] = 'H';
		string[1] = 'A';
		string[2] = 'C';
		string[3] = 'P';
		string[4] = '0' + (UCHAR)ii / 100;
		string[5] = '0' + (UCHAR)(ii %100) / 10;
		string[6] = '0' + (UCHAR)(ii % 10);
		string[7] = '\0';
		PrintLED(string);
		if( ++ii > 1000 )	ii = 0;
#endif

	// Get Index & ch
    index = READ_REGISTER_ULONG(DRV_GLOBAL_BASE + AUD_INDEX_HAC_OFFSET);
    ch    = READ_REGISTER_ULONG(DRV_GLOBAL_BASE + (sizeof(AUDIO_GLOBALS) * index) + PLAY_CH_OFFSET);

    // DMA Transmitted Interrupts Disable
	WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE + DMAC_DINTMR_OFFSET,
		READ_REGISTER_ULONG(SH7770_DMAC_REGBASE + DMAC_DINTMR_OFFSET) & ~((ULONG)1 << ch));

    // DMA Transmitted Interrupts flag Clear
    WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE + DMAC_DINTCR_OFFSET, (ULONG)1 << ch);
	READ_REGISTER_ULONG(SH7770_DMAC_REGBASE + DMAC_DINTMR_OFFSET);	// Coherency measures

    // set Playback-interrupts flag (=1)
    WRITE_REGISTER_ULONG(DRV_GLOBAL_BASE + (sizeof(AUDIO_GLOBALS) * index) + OUTINT_OFFSET, (ULONG)1);

    // set Record-interrupts flag (=0)
//    WRITE_REGISTER_ULONG(DRV_GLOBAL_BASE + (sizeof(AUDIO_GLOBALS) * index) + ININT_OFFSET, (ULONG)0);

    // Audio Playback Address != NULL ?
    if( READ_REGISTER_ULONG(DRV_GLOBAL_BASE + (sizeof(AUDIO_GLOBALS) * index) + PLAY_ADDRESS_OFFSET) != (ULONG)NULL ){

		// DMA Interrupt flag (for OEMInterruptEnable, OEMInterruptDone)
		 WRITE_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + ch, (ULONG)1);

		//
		// Playback
		//
		return SYSINTR_HAC;
    }
    else{
        //
        // Stop (Playback data empty)
        //

        // HAC0 TxDMA(Right/Left) Disable
//		WRITE_REGISTER_ULONG(HAC_REGBASE + HAC_ACR_OFFSET,
//			(READ_REGISTER_ULONG(HAC_REGBASE + HAC_ACR_OFFSET) & ~(ULONG)(HAC_ACR_DMATX16)) |
//								  (ULONG)HAC_ACR_TX12_ATOMIC );

        return SYSINTR_HAC;
    }

}

//
// HAC ISR 2
// DMA Transmitted (BusbridgeDMAC Ch1:HAC Record)
//
int	hac_isr2(
	void
	)
{
    int		index, ch;
#ifdef	DEBUG
    char string[8];
    static	int		ii = 0;

		// Output to LED (HAC Recording)
		string[0] = 'H';
		string[1] = 'A';
		string[2] = 'C';
		string[3] = 'R';
		string[4] = '0' + (UCHAR)ii / 100;
		string[5] = '0' + (UCHAR)(ii %100) / 10;
		string[6] = '0' + (UCHAR)(ii % 10);
		string[7] = '\0';
		PrintLED(string);
		if( ++ii > 1000 )	ii = 0;
#endif

	// Get Index & ch
    index = READ_REGISTER_ULONG(DRV_GLOBAL_BASE + AUD_INDEX_HAC_OFFSET);
    ch    = READ_REGISTER_ULONG(DRV_GLOBAL_BASE + (sizeof(AUDIO_GLOBALS) * index) + REC_CH_OFFSET);

    // DMA Transmitted Interrupts Disable (DINTMR)
	WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE + DMAC_DINTMR_OFFSET,
				READ_REGISTER_ULONG(SH7770_DMAC_REGBASE + DMAC_DINTMR_OFFSET) & ~((ULONG)1 << ch));

    // DMA Transmitted End flag clear (DINTCR)
    WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE + DMAC_DINTCR_OFFSET, (ULONG)1 << ch);
	READ_REGISTER_ULONG(SH7770_DMAC_REGBASE + DMAC_DINTMR_OFFSET);	// Coherency measures

    // End of Recording ?
    if( READ_REGISTER_ULONG(DRV_GLOBAL_BASE + (sizeof(AUDIO_GLOBALS) * index) + REC_ADDRESS_OFFSET) == (ULONG)NULL ){

        // HAC0 RxDMA(Right/Left) Disable
		WRITE_REGISTER_ULONG(HAC_REGBASE + HAC_ACR_OFFSET,
			(READ_REGISTER_ULONG(HAC_REGBASE + HAC_ACR_OFFSET) & ~(ULONG)(HAC_ACR_DMARX16)) |
								  (ULONG)HAC_ACR_TX12_ATOMIC );
		return SYSINTR_HAC;
    }

    // set Record-interrupts flag (=1)
    WRITE_REGISTER_ULONG(DRV_GLOBAL_BASE + (sizeof(AUDIO_GLOBALS) * index) + ININT_OFFSET, (ULONG)1);

    // set Playback-interrupts flag (=0)
//    WRITE_REGISTER_ULONG(DRV_GLOBAL_BASE + (sizeof(AUDIO_GLOBALS) * index) + OUTINT_OFFSET, (ULONG)0);

    // DMA Interrupt flag (for OEMInterruptEnable, OEMInterruptDone)
    WRITE_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + ch, (ULONG)1);

    return SYSINTR_HAC;
}
#pragma optimize("", on)