//
//  Copyright(C) Renesas Technology Corp. 2003-2004. All rights reserved.
//
//  NK Kernel for ITS-DS7 Ver.1.0.0
//
//  FILE      : hspdif_isr.c
//  CREATED   : 2003.06.20
//  MODIFIED  : 2004.09.01
//  AUTHOR    : Renesas Technology Corp.
//  HARDWARE  : RENESAS ITS-DS7
//  HISTORY   : 
//              2003.06.20
//              - Created release code.
//              2004.09.01
//              - Created release code for WCE5.0.

#include <windows.h>
#include <platform.h>
#include <sh7770.h>
#include <oalintr.h>
#include <drv_glob.h>
#include <dma.h>

#define TX_STATUS_OFFSET		0
#define RX_STATUS_OFFSET		4


#pragma optimize("", off)
//
// HSPDIF ISR 0
// HSPDIF module interrupts
//
int	hspdif_isr0(
	void
	)
{
#ifdef	DEBUG
	char string[8];
	static	int		ii = 0;

	string[0] = 'S';
	string[1] = 'P';
	string[2] = 'D';
	string[3] = 'I';
	string[4] = '0' + (UCHAR)ii / 100;
	string[5] = '0' + (UCHAR)(ii %100) / 10;
	string[6] = '0' + (UCHAR)(ii % 10);
	string[7] = '\0';
	PrintLED(string);
	if( ++ii > 1000 )	ii = 0;
#endif

    return SYSINTR_NOP;
}

//
// HSPDIF ISR 1
// DMA Transmitted (BusbridgeDMAC Ch2:HSPDIF Playback)
//
int	hspdif_isr1(
	void
	)
{
#ifdef	DEBUG
    char string[8];
    static	int		ii = 0;

	string[0] = 'S';
	string[1] = 'P';
	string[2] = 'D';
	string[3] = 'I';
	string[4] = 'P';
	string[5] = '0' + (UCHAR)(ii %100) / 10;
	string[6] = '0' + (UCHAR)(ii % 10);
	string[7] = '\0';
	PrintLED(string);
	if( ++ii > 100 )	ii = 0;
#endif

	if(	!(READ_REGISTER_ULONG(SH7770_DMAC_REGBASE + DMAC_DINTSR_OFFSET) & (0x00000001 << CH_TX_HSPDIF))){
	    return SYSINTR_NOP;
	}

    // DMA Transmitted Interrupts Disable
	WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE + DMAC_DINTMR_OFFSET,
		READ_REGISTER_ULONG(SH7770_DMAC_REGBASE + DMAC_DINTMR_OFFSET) & ~((ULONG)1 << CH_TX_HSPDIF));

	// DMA Transmitted Interrupts flag Clear
	WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE + DMAC_DINTCR_OFFSET, (ULONG)1 << CH_TX_HSPDIF);
	READ_REGISTER_ULONG(SH7770_DMAC_REGBASE + DMAC_DINTMR_OFFSET);		// Coherency measures

    // set tx-interrupts flag (=1)
    WRITE_REGISTER_ULONG(SPDIF_GLOBAL_BASE + TX_STATUS_OFFSET, (ULONG)1);

	// DMA Interrupt flag (for OEMInterruptEnable, OEMInterruptDone)
	 WRITE_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + CH_TX_HSPDIF, (ULONG)1);

    return SYSINTR_HSPDIF;

}

//
// HSPDIF ISR 2
// DMA Transmitted (BusbridgeDMAC Ch3:HSPDIF Record)
//
int	hspdif_isr2(
	void
	)
{
#ifdef	DEBUG
    char string[8];
    static	int		ii = 0;

	string[0] = 'S';
	string[1] = 'P';
	string[2] = 'D';
	string[3] = 'I';
	string[4] = 'R';
	string[5] = '0' + (UCHAR)(ii %100) / 10;
	string[6] = '0' + (UCHAR)(ii % 10);
	string[7] = '\0';
	PrintLED(string);
	if( ++ii > 100 )	ii = 0;
#endif

	if(	!(READ_REGISTER_ULONG(SH7770_DMAC_REGBASE + DMAC_DINTSR_OFFSET) & (0x00000001 << CH_RX_HSPDIF))){
	    return SYSINTR_NOP;
	}

    // DMA Transmitted Interrupts Disable
	WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE + DMAC_DINTMR_OFFSET,
		READ_REGISTER_ULONG(SH7770_DMAC_REGBASE + DMAC_DINTMR_OFFSET) & ~((ULONG)1 << CH_RX_HSPDIF));

	// DMA Transmitted Interrupts flag Clear
	WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE + DMAC_DINTCR_OFFSET, (ULONG)1 << CH_RX_HSPDIF);
	READ_REGISTER_ULONG(SH7770_DMAC_REGBASE + DMAC_DINTMR_OFFSET);		// Coherency measures

    // set rx-interrupts flag (=1)
    WRITE_REGISTER_ULONG(SPDIF_GLOBAL_BASE + RX_STATUS_OFFSET, (ULONG)1);

	// DMA Interrupt flag (for OEMInterruptEnable, OEMInterruptDone)
	 WRITE_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + CH_RX_HSPDIF, (ULONG)1);

	return SYSINTR_HSPDIF;
}
#pragma optimize("", on)