//
//  Copyright(C) Renesas Technology Corp. 2005. All rights reserved.
//
// LAN91C111 Network Driver for ITS-DS7
//
// FILE     : smsc111common.h
// CREATED  : 2005.05.10
// MODIFIED : 
// AUTHOR   : Renesas Technology Corp.
// HARDWARE : RENESAS ITS-DS7
// HISTORY  : 
//            2005.05.10
//            - Created release code.
//                (based on SMSC100FD NETCARD driver for PUBLIC for WCE5.0)

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//

#define   SMSC111_REG_SIZE           0x0020

//
// SMSC111 Bank 0 Register Space
//
#define	TCR 				0			// Transmit Control Register
#define TCR_ENABLE			0x0001		// If this is 1, the transmitter is enabled
#define	TCR_LOOP			0x0002		// Internal loopback mode
#define	TCR_FORCOL			0x0004		// Force Collision
#define	TCR_PAD_ENABLE		0x0080		// Pad short packets to 64 bytes
#define TCR_NOCRC			0x0100		// No CRC appended
#define	TCR_MON_CSN			0x0400		// Monitor the carrier status
#define TCR_FDUPLX		 	0x0800		// Full Duplex
#define TCR_STP_SQET		0x1000		// Signal quality errors stop the transmitter
#define TCR_EPH_LOOP		0x2000		// EPH loopback mode
#define TCR_SWFDUP			0x8000		// Switched Full Duplex Mode

#define TX_STATUS			2			// Transmit status (also known as the Ethernet Status)
#define TS_SUCCESS			0x0001		// Transmission successful
#define TS_SINGLE			0x0002		// Single Collision
#define TS_MULTIPLE			0x0004		// Multiple Collisions
#define TS_LTX_MULTI		0x0008		// Last packet transmitted was a multicast packet
#define TS_16COL			0x0010		// 16 collisions, transmitter disabled
#define TS_SQET				0x0020		// Signal qualite error test
#define TS_LTX_BROAD		0x0040		// Last packet transmitted was a broadcast packet
#define TS_DEFER			0x0080		// Transmission deferred
#define TS_LATCOL			0x0200		// Late Collision detected
#define TS_LOSTCAR			0x0400		// Lost carrier
#define TS_EXCESSIVE		0x0800		// Excessive deferral
#define TS_ROLLOVER			0x1000		// Counter Rollover
#define ES_RXOVERRUN		0x2000		// Receiver overrun
#define ES_LINK_OK			0x4000		// Link integrity OK
#define ES_TXOVERRUN		0x8000		// Transmitter overrun

#define	RCR					4			// Receive Control Register
#define RCR_ABORT			0x0001		// Receive frame aborted
#define	RCR_PROMISC			0x0002		// Promiscuous mode enable
#define RCR_ALMUL			0x0004		// Receive all multicast packets
#define RCR_ENABLE			0x0100		// Receiver enable
#define	RCR_STRIP_CRC		0x0200		// Strips CRC enable
#define RCR_ABORT_ENABLE	0x2000		// Abort on collision enable
#define RCR_FILTER			0x4000		// Filter Carrier enable
#define RCR_SOFTRESET		0x8000		// Software Reset

#define	COUNTER				6			// Counter Register
#define	MIR					8			// Memory Information Register

#define	RPCR				10			// Receive/PHY Control Register
#define RPCR_LS0B			0x0004		// LEDB select signal enable
#define RPCR_LS1B			0x0008		// 
#define RPCR_LS2B			0x0010		// 
#define RPCR_LS0A			0x0020		// LEDA select signal enable
#define RPCR_LS1A			0x0040		// 
#define RPCR_LS2A			0x0080		// 
#define RPCR_ANEG			0x0800		// Auto-Negotiation mode select
#define RPCR_DPLX			0x1000		// Duplex select
#define RPCR_SPEED			0x2000		// Speed select input

#define	BANK_SELECT			14			// Bank Select Register (mirrored in every bank)

//
// SMSC111 Bank 1 Register Space
//
#define CONFIG				0			// Configuration Register
#define CFG_EXTPHY			0x0200		// External PHY enabled
#define CFG_GPCNTRL			0x0400		// General purpose output port
#define CFG_NOWAIT			0x1000		// No additional wait states
#define CFG_EPH_POWER_EN	0x8000		// Power transition(EPH low power)
#define CFG_RESERVE			0x20B1		// Reserved

#define	BASE				2			// Base Address Register
#define	ADDR0				4			// MAC Address 0 and 1
#define	ADDR1				6			// MAC Address 2 and 3
#define	ADDR2				8			// MAC Address 4 and 5
#define	GENERAL				10			// General purpose register

#define	CONTROL				12			// Control Register
#define CTL_STORE			0x0001		// Store to EEPROM
#define CTL_RELOAD			0x0002		// Read from EEPROM
#define CTL_EEPROM			0x0004		// EEPROM Select
#define CTL_ONE_1			0x0010		// Always 1
#define	CTL_TE_ENABLE		0x0020		// Transmit Error enable
#define	CTL_CR_ENABLE		0x0040		// Counter rollover enable
#define	CTL_LE_ENABLE		0x0080		// Link Error enable
#define CTL_ONE_2			0x0100		// Always 1
#define CTL_AUTO_RELEASE	0x0800		// Auto Release memory
#define CTL_RCV_BAD			0x4000		// Receive bad CRC packets

//
// SMSC111 Bank 2 Register Space
//
#define MMU_CMD				0			// MMU Command Register
#define MC_BUSY				1			// MMU is busy
#define MC_NOP				0x00		// MMU No Operation Command
#define	MC_ALLOC			0x20	  	// MMU Allocate Memory Command
#define	MC_RESET			0x40		// MMU Reset Command
#define	MC_REMOVE			0x60		// MMU Remove Current RX Packet Command
#define MC_RELEASE		  	0x80		// MMU Remove and Release Current RX Packet Command
#define MC_FREEPKT  		0xA0	  	// MMU Release Packet in PNR Command
#define MC_ENQUEUE			0xC0		// MMU Enqueue the Transmit Packet Command

#define	PNR_ARR				2			// Packet Number Register and Allocated Result Register

#define FIFO_PORTS			4			// FIFO Ports register
#define FP_RXEMPTY			0x8000		// Receive FIFO Empty status
#define FP_TXEMPTY			0x0080		// Transmit FIFO Empty status

#define	POINTER				6			// Pointer Register
#define PTR_NOT_EMPTY		0x0800		// Write Data FIFO is not empty
#define PTR_ETEN			0x1000		// Early Transmit Underrun Detection
#define PTR_READ			0x2000		// Read operation follows
#define	PTR_AUTOINC			0x4000		// Auto increment pointer after data accesses
#define	PTR_RCV				0x8000		// Receive data area

#define	DATA_1				8			// Data Transfer Register
#define	DATA_2				10			// Data transfer Register

#define	INTERRUPT_REGISTER	12			// Interrupt Control Register (Status, Ack, and Mask)
// Interrupt Status,Interrupt Acknowledge
#define	IS_RCV_INT			0x0001		// Receive Interrupt
#define	IS_TX_INT			0x0002		// Transmit Complete Interrupt
#define	IS_TXEMPTY_INT		0x0004		// Transmit FIFO Empty Interrupt
#define	IS_ALLOC_INT		0x0008		// MMU Allocation Complete Interrupt
#define	IS_OVRN_INT			0x0010		// Receive Overrun Interrupt
#define IS_EPH_INT			0x0020		// EPH Interrupt
#define IS_ERCV_INT			0x0040		// Early Receive Interrupt
#define IS_MDINT			0x0080		// Status Change Interrupt
										// PHY MI Register 18 (Serial Port Status Output Register)
										//   LNKFAIL,LOSSSYNC,CWRD,SSD,ESD,PROL,JAB,SPDDET,DPLXDET
// Interrupt Mask
#define IM_RCV_INT			0x0100		// Receive Interrupt
#define	IM_TX_INT			0x0200		// Transmit Complete Interrupt
#define	IM_TX_EMPTY_INT		0x0400		// Transmit FIFO Empty Interrupt
#define	IM_ALLOC_INT		0x0800		// MMU Allocation Complete Interrupt
#define	IM_RX_OVRN_INT		0x1000		// Receive Overrun Interrupt
#define	IM_EPH_INT			0x2000		// EPH Interrupt
#define	IM_ERCV_INT			0x4000		// Early Receive Interrupt
#define IM_MDINT			0x8000		// Status Change Interrupt
										// PHY MI Register 18 (Serial Port Status Output Register)
										//   LNKFAIL,LOSSSYNC,CWRD,SSD,ESD,PROL,JAB,SPDDET,DPLXDET

//
// SMSC111 Bank 3 Register Space
//
#define	MULTICAST1			0			// Multicast Bits
#define	MULTICAST2			2			// Multicast Bits
#define	MULTICAST3			4			// Multicast Bits
#define	MULTICAST4			6			// Multicast Bits

#define	MGMT				8			// Management Register
#define	MGMT_MDO			0x0001		// MII Data Out
#define MGMT_MDI			0x0002		// MII Data In
#define MGMT_MCLK			0x0004		// MII Clock
#define MGMT_MDOE			0x0008		// MII Data Out Enable

#define	REVISION			10			// Chip Revision Register
										// 3:"SMC91C90/91C92"
										// 4:"SMC91C94"
										// 5:"SMC91C95"
										// 6:"SMC91C96"
										// 7:"SMC91C100" 
										// 8:"SMC91C100FD"
										// 9:"SMC91C110/91C111"

#define	ERCV				12			// Early RCV Register
#define ERCV_RCV_DISCRD		0x0080		
#define ERCV_THRESHOLD_MASK	0x001F		

//
// Receive Frame status word
//
#define RS_ALGNERR			0x8000		// Byte alignment error
#define RS_BROADCAST		0x4000		// Broadcast frame
#define RS_BADCRC			0x2000		// Bad CRC
#define RS_ODDFRAME			0x1000		// Odd number of bytes
#define RS_TOOLONG			0x0800		// Mammoth packet
#define RS_TOOSHORT			0x0400		// Runt packet
#define RS_MULTICAST		0x0001		// Multicast packet

//
// Receive Frame Control word
//
#define RC_ODDFRAME			0x2000		// Odd number of bytes

//
// Transmit Frame Control word
//
#define TC_APPENDCRC		0x1000		// Append CRC
#define TC_ODDFRAME			0x2000		// Odd number of bytes

//
// These values are written to the bank select register to change banks.
//
#define BANK0				0x3300		// Bank 0
#define BANK1				0x3301		// Bank 1
#define BANK2				0x3302		// Bank 2
#define BANK3				0x3303		// Bank 3

//
// Select the register bank.
//
//#define SelectBank(Bank) WriteWord (BANK_SELECT, Bank)

//
// EEPROM definitions
//
#define EEPROM_ADDRESSES 64

//
// PHY definitions
//
#define PHY_ADDRESSES 32

//
// Bits related to the MII interface
//
#define PHY_ADDRESS			0
#define MIIREG_READ			((ULONGLONG)0xffffffff60000000L)
#define MIIREG_WRITE		((ULONGLONG)0xffffffff50020000L)
#define MIIREG_INDEX_BIT	18
#define MIIREG_INDEX_MASK	((ULONGLONG)0x1f << MIIREG_INDEX_BIT)
#define MIIREG_PHYADDR_BIT	23
#define MIIREG_PHYADDR_MASK	((ULONGLONG)0x1f << MIIREG_PHYADDR_BIT)
#define MIIREG_CONTENT_MASK	((ULONGLONG)0x000000000000ffffL)
#define MIIREG_NEXTBIT_MASK	((ULONGLONG)0x8000000000000000L)
#define MIIREG_NEXTBIT_BIT	63

//
// Registers in the PHY
//
#define PHY_CONTROL			0
#define PHY_STATUS			1
#define PHY_ID0				2
#define PHY_ID1				3
#define PHY_ANADVERTISE		4
#define PHY_ANCAPABILITY	5
#define PHY_CONFIG1			16
#define PHY_CONFIG2			17
#define PHY_STATOUT			18
#define PHY_MASK			19
//
// Bits in the PHY_CONTROL register
//
#define PHY_CTRL_RESET		0x8000
#define PHY_CTRL_LOOPBACK	0x4000
#define PHY_CTRL_SPEED		0x2000
#define PHY_CTRL_ANENABLE	0x1000
#define PHY_CTRL_PWRDWN		0x0800
#define PHY_CTRL_ISOLATION	0x0400
#define PHY_CTRL_ANRESTART	0x0200
#define PHY_CTRL_DUPLEX		0x0100
//
// Bits in the PHY_STATUS register
//
#define PHY_STAT_LINK		0x0004
#define PHY_STAT_ANCOMPLETE	0x0020
//
// Bits in the PHY_ANADVERTISE/PHY_ANCAPABILITY register
//
#define PHY_ANA_T4			0x0200	// 100BASE-T4
#define PHY_ANA_100FDX		0x0100	// 100BASE-TX Full Duplex Capable
#define PHY_ANA_100HDX		0x0080	// 100BASE-TX Half Duplex Capable
#define PHY_ANA_10FDX		0x0040	// 10BASE-T Full Duplex Capable
#define PHY_ANA_10HDX		0x0020	// 10BASE-T Half Duplex Capable
//
// Bits in the PHY_IDENTIFIER register
//
#define PHY_ID0_DEFAULT		0x0016
#define PHY_ID1_DEFAULT		0xf840
//
// Bits in the PHY_MASK register
//
#define PHY_MASK_MDPLDT		0x0040	// duplex detect
#define PHY_MASK_MSPDDT		0x0080	// 100/10 speed detect
#define PHY_MASK_MJAB		0x0100	// jabber detect
#define PHY_MASK_MRPOL		0x0200	// reverse polarity detect
#define PHY_MASK_MESD		0x0400	// end of stream error
#define PHY_MASK_MSSD		0x0800	// start of stream error
#define PHY_MASK_MCWRD		0x1000	// codeword error
#define PHY_MASK_MLOSSSYN	0x2000	// descrambler loss of synchronization detect
#define PHY_MASK_MLNKFAIL	0x4000	// link fail detect
#define PHY_MASK_MINT		0x8000	// interrupt detect


// This is the format for the ethernet frame that is transmitted on the wire
#pragma pack (push, 1)
typedef struct _EthernetFrameHeader
	{
	UINT16 wDestMAC[3];
	UINT16 wSrcMAC[3];
	UINT16 wFrameType;
	// Then the data
	// After the data is a 4 byte CRC
	} EthernetFrameHeader;
#pragma pack (pop) 

//
// Layout of the EEPROM contents
// NOTE: The layout is designed to create the proper address offset into the EEPROM.
//
#pragma pack (push, 1)
typedef struct _SMSC111EEPROM
	{
	UCHAR ucConfigReg;			// Contents of CONFIG register after reset
	UCHAR ucBaseReg;			// Contents of BASE register after reset
	UCHAR ucReserved0[2+4*7];	// Reserved
	UCHAR ucMacAddress[3];		// MAC address
	UCHAR ucIp[2];				// IP address
	UCHAR ucSubnetMask[2];		// Subnet Mask
	UCHAR ucReserved1[64-38];	// Reserved
	} SMSC111EEPROM, *PSMSC111EEPROM;
#pragma pack (pop)