//
//      Copyright(C) Renesas Technology Corp. 1999-2005. All rights reserved.
//
//      WaveDev Driver for ITS-DS7
//
//----------------------------------------------------------------------------
//
// FILE      : HAC.H
// CREATED   : 1999.04.26 (for HD64465 on PFM-DS6)
// MODIFIED  : 2005.04.26
// AUTHOR    : Renesas Technology Corp.
// HARDWARE  : RENESAS ITS-DS7
// FUNCTION  : MDD-PDD interface layer of waveform audio driver
// HISTORY   : 
//             2003.06.20
//              - Created release code.
//                (based on WaveDev driver for ITS-DS6 Ver.2.2.0 for WCE4.1)
//             2004.09.01
//              - Created release code for WCE5.0.
//             2005.04.26
//              - Modified PCM data size from 20bit to 16bit Packed RX DMA.

#include <windows.h>
#include <types.h>
#include <memory.h>
#include <excpt.h>
#include <waveddsi.h>
#include <wavedbg.h>
#include <mmsystem.h>

#include "shx.h"
#include "sh7770.h"
#include "platform.h"
#include "dma.h"

// Offset
#define HAC_CR_OFFSET			0x0008
#define HAC_CSAR_OFFSET			0x0020
#define HAC_CSDR_OFFSET			0x0024
#define HAC_PCML_OFFSET			0x0028
#define HAC_PCMR_OFFSET			0x002C
#define HAC_TIER_OFFSET			0x0050
#define HAC_TSR_OFFSET			0x0054
#define HAC_RIER_OFFSET			0x0058
#define HAC_RSR_OFFSET			0x005C
#define HAC_ACR_OFFSET			0x0060

// Bit define
// Control and Status Register (CR)
#define HAC_CR_CR				0x00008000		// Codec Ready(15)
#define HAC_CR_CDRT				0x00000800		// Cold Reset for HAC(11)
#define HAC_CR_WMRT				0x00000400		// Warm Reset for HAC(10)
#define HAC_CR_ST				0x00000020		// Start Transfer(5)
#define HAC_CR_RESERVE			0x00000200		// Reserve

// Command/Status Address Register (CSAR)
#define HAC_CSAR_RW				0x00080000		// Codec Read/Write Comand(19)

// Transmit Interrupt Enable Register (TIER)
#define HAC_ATIER_PLTFRQIE		0x20000000		// PCML TX REQUEST Interrup Enable(29)
#define HAC_ATIER_PRTFRQIE		0x10000000		// PCMR TX REQUEST Interrup Enable(28)
#define HAC_ATIER_PLTFUNIE		0x00000200		// PCML TX Underrun Interrup Enable(9)
#define HAC_ATIER_PRTFUNIE		0x00000100		// PCMR TX Underrun Interrup Enable(8)

// TX Status Register (TSR)
#define HAC_TSR_CMDAMT			0x80000000		// Command Address Empty(31)
#define HAC_TSR_CMDDMT			0x40000000		// Command Data Empty(30)
#define HAC_TSR_PLTFRQ			0x20000000		// PCML TX Request(29)
#define HAC_TSR_PRTFRQ			0x10000000		// PCMR TX Request(28)
#define HAC_TSR_PLTFUN			0x00000200		// PCML TX Underrun(9)
#define HAC_TSR_PRTFUN			0x00000100		// PCMR TX Underrun(8)

// Receive Interrupt Enable Register (RIER)
#define HAC_RIER_STARYIE		0x00400000		// Status Address Ready Interrup Enable(22)
#define HAC_RIER_STDRYIE		0x00200000		// Status Data Ready Interrupt Enable(21)
#define HAC_RIER_PLRFRQIE		0x00100000		// PCML RX Request Interrupt Enable(20)
#define HAC_RIER_PRRFRQIE		0x00080000		// PCMR RX Request Interrupt Enable(19)
#define HAC_RIER_PLRFOVIE		0x00002000		// PCML RX Overrun Interrupt Enable(13)
#define HAC_RIER_PRRFOVIE		0x00001000		// PCMR RX Overrun Interrupt Enable(12)

// RX Status Register (RSR)
#define HAC_RSR_STARY			0x00400000		// Status Address Ready(22)
#define HAC_RSR_STDRY			0x00200000		// Status Data Ready(21)
#define HAC_RSR_PLRFRQ			0x00100000		// PCML RX Request(20)
#define HAC_RSR_PRRFRQ			0x00080000		// PCMR RX Request(19)
#define HAC_RSR_PLRFOV			0x00002000		// PCML RX Overrun(13)
#define HAC_RSR_PRRFOV			0x00001000		// PCMR RX Overrun(12)

// HAC Control Register (ACR)
#define HAC_ACR_DMARX16			0x40000000		// 16 bit RX DMA Enable(30)
#define HAC_ACR_DMATX16			0x20000000		// 16 bit TX DMA Enable(29)
#define HAC_ACR_TX12_ATOMIC		0x04000000		// TX slots 1 and 2 atomic control(26)
#define HAC_ACR_RXDMAL_EN		0x01000000		// RX DMA Left Enable(24)
#define HAC_ACR_TXDMAL_EN		0x00800000		// TX DMA Left Enable(23)
#define HAC_ACR_RXDMAR_EN		0x00400000		// RX DMA Right Enable(22)
#define HAC_ACR_TXDMAR_EN		0x00200000		// TX DMA Right Enable(21)
#define HAC_ACR_RESERVE			0x80000000		// Reserve

#define HAC_R_DMA_PAGE_SIZE		0x00001000

// HAC Base Address
static  PBYTE	pHAC_RegBase;

// HAC Registers
PVULONG pHAC_CR;
PVULONG pHAC_CSAR;
PVULONG pHAC_CSDR;
PVULONG pHAC_PCML;
PVULONG pHAC_PCMR;
PVULONG pHAC_TIER;
PVULONG pHAC_TSR;
PVULONG pHAC_RSR;
PVULONG pHAC_ACR;

BOOL CODEC_AD;
ULONG   ulCurrentPlaySamplingRate;
ULONG   ulCurrentRecSamplingRate;

// Control data for CODEC
ULONG   ulMasterVol;
ULONG   ulPCMoutVol;
ULONG   ulRecGain;
ULONG   ulRecSel;
ULONG   ulMicVol;
ULONG   ulLineInVol;

BOOL Wait_CSAR(void);
BOOL Wait_CSDR(void);
BOOL Wait_AddrRdy(void);
BOOL Wait_DataRdy(void);
BOOL Wait_Status(ULONG);
BOOL Write_codec(ULONG, ULONG);
BOOL private_ChangeSampleRate(ULONG);
BOOL private_ChangeRecSampleRate(ULONG);
extern PBYTE GetVirtualAddressOfUncachedMemory( PVOID, ULONG, char *);
extern BOOL dma_Init(int, PDMA_INFO *);
extern BOOL dma_Deinit(PDMA_INFO);
extern BOOL dma_SetPort(PDMA_INFO, DWORD);
extern BOOL dma_SetPage(PDMA_INFO, DWORD, DWORD, DWORD, DWORD);
extern BOOL dma_SetControl(PDMA_INFO, DWORD);
extern BOOL dma_SetCommand(PDMA_INFO, DWORD);
extern BOOL dma_InterruptEnable(PDMA_INFO);
extern BOOL dma_InterruptDisable(PDMA_INFO);
extern BOOL dma_Stop(PDMA_INFO);
extern BOOL dma_IsFinished(PDMA_INFO/*, DWORD*/);