//
//  Copyright(C) Renesas Technology Corp. 1999-2004. All rights reserved.
//
//  Serial driver for ITS-DS7
//
//  FILE      : scif.h
//  CREATED   : 2002.06.26
//  MODIFIED  : 2004.09.01
//  AUTHOR    : Renesas Technology Corp.
//  HARDWARE  : RENESAS ITS-DS7
//  HISTORY   : 
//              2002.06.20
//              - Created release code.
//                (based on ITS-DS4 Source Kit Ver.1.2.0 for WCE 4.2)
//              2004.09.01
//              - Created release code for WCE5.0.
//
#include "dma.h"
#include <serhw.h>

#ifndef _SCIF_H_
#define _SCIF_H_

// Register defines, the regs are defined in project.h, these are the bits 
// SMR (Serial Mode Register)
#define SCIF_SMR_ASYNC				0x0000	// ASynchronous Mode
#define SCIF_SMR_SYNC				0x0080	// Synchronous Mode
#define SCIF_SMR_8BIT				0x0000	// 8 Bit Data
#define SCIF_SMR_7BIT				0x0040	// 7 Bit Data
#define SCIF_SMR_PE					0x0020	// Parity Enable
#define SCIF_SMR_EVEN_PAR			0x0000	// Even Parity
#define SCIF_SMR_ODD_PAR			0x0010	// Odd Parity
#define SCIF_SMR_1STOP				0x0000	// 1 Stop Bit
#define SCIF_SMR_2STOP				0x0008	// 2 Stop Bits
#define SCIF_SMR_CKS_1				0x0000	// Clock Select P0
#define SCIF_SMR_CKS_4				0x0001	// Clock Select P0/4
#define SCIF_SMR_CKS_16				0x0002	// Clock Select P0/16
#define SCIF_SMR_CKS_64				0x0003	// Clock Select P0/64

// SCR (Serial Control Register)
#define SCIF_SCR_TIE				0x0080	// Transmit Interrupt Enable
#define SCIF_SCR_RIE				0x0040	// Receive Interrupt Enable
#define SCIF_SCR_TE					0x0020	// Transmit Enable
#define SCIF_SCR_RE					0x0010	// Receive Enable
#define SCIF_SCR_REIE				0x0008	// Receive Error Interrupt Enable
#define SCIF_SCR_TOIE				0x0004	// Timeout Interrupt Enable
#define SCIF_SCR_CKE_0				0x0000	// Internal Clock, SCK Off
#define SCIF_SCR_CKE_1				0x0001	// Internal Clock, SCK Out
#define SCIF_SCR_CKE_2				0x0002	// External Clock, SCK In

// SSR (Serial Status Register)
#define SCIF_SSR_PERN				0xf000	// Number of Parity error
#define SCIF_SSR_FERN				0x0f00	// Number of Framing error
#define SCIF_SSR_ER					0x0080	// Receive Error
#define SCIF_SSR_TEND				0x0040	// Transmit End
#define SCIF_SSR_TDFE				0x0020	// Transmit FIFO Data Empty
#define SCIF_SSR_BRK				0x0010	// Break Detect
#define SCIF_SSR_FER				0x0008	// Framing Error
#define SCIF_SSR_PER				0x0004	// Parity Error
#define SCIF_SSR_RDF				0x0002	// Receive FIFO Data Full
#define SCIF_SSR_DR					0x0001	// Receive Data Ready

// FCR (Fifo Control Register)
#define SCIF_FCR_RSTRG_1			0x0100	// RTS Active Trigger 1
#define SCIF_FCR_RSTRG_4			0x0200	// RTS Active Trigger 4
#define SCIF_FCR_RSTRG_6			0x0300	// RTS Active Trigger 6
#define SCIF_FCR_RSTRG_8			0x0400	// RTS Active Trigger 8
#define SCIF_FCR_RSTRG_10			0x0500	// RTS Active Trigger 10
#define SCIF_FCR_RSTRG_12			0x0600	// RTS Active Trigger 12
#define SCIF_FCR_RSTRG_14			0x0700	// RTS Active Trigger 14
#define SCIF_FCR_RSTRG_15			0x0000	// RTS Active Trigger 15
#define SCIF_FCR_RTRG_1				0x0000	// Receive FIFO Trigger 1
#define SCIF_FCR_RTRG_4				0x0040	// Receive FIFO Trigger 4
#define SCIF_FCR_RTRG_8				0x0080	// Receive FIFO Trigger 8
#define SCIF_FCR_RTRG_14			0x00C0	// Receive FIFO Trigger 14
#define SCIF_FCR_TTRG_0				0x0030	// Transmit FIFO Trigger 0
#define SCIF_FCR_TTRG_2				0x0020	// Transmit FIFO Trigger 2
#define SCIF_FCR_TTRG_4				0x0010	// Transmit FIFO Trigger 4
#define SCIF_FCR_TTRG_8				0x0000	// Transmit FIFO Trigger 8
#define SCIF_FCR_MCE				0x0008	// Modem Control Enable
#define SCIF_FCR_TFRST				0x0004	// Reset Transmit FIFO Data Register
#define SCIF_FCR_RFRST				0x0002	// Reset Receive FIFO Data Register
#define SCIF_FCR_LOOP				0x0001	// Enable Loop Back Teset

// SPTR (Serial Port Register)
#define SCIF_SPTR_RTSIO				0x0080	// 
#define SCIF_SPTR_RTS				0x0040	// 
#define SCIF_SPTR_CTSIO				0x0020	// 
#define SCIF_SPTR_CTS				0x0010	// 
#define SCIF_SPTR_SCKIO				0x0008	// 
#define SCIF_SPTR_SCK				0x0004	// 
#define SCIF_SPTR_SPBIO				0x0002	// 
#define SCIF_SPTR_SPB				0x0001	// 

// LST (Line Status Register)
#define SCIF_LSR_ORER				0x0001	// Overrun error
#define SCIF_LSR_TO				0x0004	// Timeout 

#define SCIF_SCSMR_EDGEN_LV			0x0200 // twice (edge + level) sampling Rx3
#define SCIF_SCSMR_LOOP_ON			0x0100 // Tx3 -> Rx3 Poop Back
#define SCIF_SCSMR_IRMOD_ON			0x0080 // SCIF3 is used as IrDA 

#define SCIF_BRG_DL                     0x00000030 // for SCIF CH0, SCIF CH2 - CH8
#define SCIF_BRG_CKS                    0x00000034 // for SCIF CH0, SCIF CH2 - CH8
#define SCIF_TESTCTL                    0x00000040 // for SCIF CH5
#define SCIF_TESTRS                     0x00000044 // for SCIF CH5
#define SCIF_IRDA_SCSMR                 0x00000040 // for SCIF CH6

/* We use a callback for serial events */
typedef VOID		(*EVENT_FUNC)(PVOID Arg1, ULONG Arg2);
#ifndef PAIRS
typedef struct	__PAIRS {
    ULONG   Key;
    ULONG   AssociatedValue;
} PAIRS, *PPAIRS;
#endif
#ifndef LOOKUP_TBL
typedef struct __LOOKUP_TBL {
    ULONG   Size;
    PPAIRS  Table;
} LOOKUP_TBL, *PLOOKUP_TBL;
#endif

typedef struct __LS_SERIAL_INFO
{
    /* Store volatile pointers to each USART register */
    volatile USHORT	*pSMR;	// Pointer To Serial Mode Register
    volatile BYTE		*pBRR;	// Pointer To Bit Rate Register
    volatile USHORT	*pSCR;	// Pointer To Serial Control Register
    volatile BYTE		*pFTDR;	// Pointer To Transmit FIFO Data Register
    volatile USHORT	*pFSR;	// Pointer To Serial Status Register
    volatile BYTE		*pFRDR;	// Pointer To Receive FIFO Data Register
    volatile USHORT	*pFCR;	// Pointer To FIFO Control Register
    volatile USHORT	*pFDR;	// Pointer To Number of FIFO Data Register
    volatile USHORT	*pSPTR;	// Pointer To Serial Port Register
    volatile USHORT	*pLSR;	// Line Status Register

    volatile USHORT	*pBRGDL;	// Baudrate Generator DL
    volatile USHORT	*pBRGCKS;// Baudrate Generator CKS

    volatile USHORT	*pSCSMR;	// IrDA
    
    /* We have an event callback into the MDD */
    EVENT_FUNC	EventCallback;	/* This callback exists in MDD */
    PVOID       pMddHead;		/* This is the first parm to callback */
        
    /* Keep a copy of DCB since we rely on many of its parms */
    DCB         dcb;			/* Device Control Block(copy of DCB in MDD) */
    
	/* And the same thing applies for CommTimeouts */
    COMMTIMEOUTS CommTimeouts;  /* Copy of CommTimeouts structure */
	ULONG		OpenCount;	    /* Count of simultaneous opens. */
	PLOOKUP_TBL	pBaudTable;		// Pointer to Baud Table
    ULONG		DroppedBytes;	/* Number of dropped bytes */
    HANDLE		FlushDone;		/* Handle to flush done event. */
    CRITICAL_SECTION	TransmitCritSec; /* Protects UART TX FIFO from simultaneous access */
    CRITICAL_SECTION	RegCritSec; // @field Protects UART 
    BOOL		PowerDown;      // did we power down the chip
    BOOL		bSuspendResume; // Indicate Suspend/Resume happens
	BOOL		CTSFlowOff;		/* Flag - CTS flow control state. */
    BOOL		DSRFlowOff;		/* Flag - DSR flow control state. */
	BOOL		AddTXIntr;		/* Flag - Fake a TX intr. */
    COMSTAT		Status; 		/* Bitfield representing Win32 comm status. */
    ULONG		CommErrors;		/* Bitfield representing Win32 comm error status. */
    ULONG		ModemStatus;	/* Bitfield representing Win32 modem status. */
	BOOL		CommCharInQueue; /* there is a command char in the queue */
	COMMPROP	CommProp;		/* common Properties Structure */
	int			LastClose;
	BOOL		fIRMode;

	PVBYTE		pBaseAddress;
	PVBYTE		pDMABaseAddress;

	BOOL		bFirstBaudRate;

    USHORT		SMR;	// Serial Mode Register
    USHORT		BRR;	// Bit Rate Register
    USHORT		SCR;	// Serial Control Register
    USHORT		FCR;	// FIFO Control Register
    USHORT		SPTR;	// Serial Port Register
    USHORT		BRGDL;	// Baudrate Generator DL
    USHORT		BRGCKS; // Baudrate Generator CKS
    USHORT		SCSMR;	// IrDA

//	PUCHAR		pvIR;

    PDMA_INFO	pTxDma;			// DMA Transfer Infomation 
    PDMA_INFO	pRxDma;			// DMA Receive Infomation
    PBYTE	pTxBuff;		// DMA Transfer Buffer
    PBYTE	pRxBuff;		// DMA Receive Buffer
    ULONG	ulRxDmaRegBase;		// DMA Receive Register Base Address
    ULONG	ulRxDmaBuffBase1;		// DMA Receive Buffer Base Address (Page1)
    ULONG	ulRxDmaBuffBase2;		// DMA Receive Buffer Base Address (Page2)
    ULONG	ulRxDmaBuffSize;		// DMA Receive Buffer Size 
    DWORD	dwRxDmaPort;		// DMA Receive Port 
    ULONG	ulReceiveDmaBufferPointer;	// DMA Receive Buffer Read Pointer
    PHWOBJ      pHWObj;         // @field Pointer to PDDs HWObj structure

    } SCIF_INFO, *PSCIF_INFO;


ULONG	SCIF_Close(PVOID);
ULONG	SCIF_Deinit(PVOID);
VOID	SCIF_ClearDTR(PVOID);
VOID	SCIF_SetDTR(PVOID);
VOID	SCIF_ClearRTS(PVOID);
VOID	SCIF_SetRTS(PVOID);
VOID	SCIF_ClearBreak(PVOID);
VOID	SCIF_SetBreak(PVOID);
BOOL	SCIF_SetBaudRate(PVOID, ULONG);
BOOL	SCIF_SetByteSize(PVOID, ULONG);
BOOL	SCIF_SetParity(PVOID, ULONG);
BOOL	SCIF_SetStopBits(PVOID, ULONG);
ULONG	SCIF_GetRxBufferSize(PVOID);
PVOID	SCIF_GetRxStart(PVOID);
INTERRUPT_TYPE	SCIF_GetInterruptType(PVOID);
ULONG	SCIF_RxIntr(PVOID, PUCHAR, ULONG *);
VOID	SCIF_TxIntr(PVOID);
VOID	SCIF_LineIntr(PVOID);
VOID	SCIF_OtherIntr(PVOID);
ULONG	SCIF_GetStatus(PVOID, LPCOMSTAT);
VOID	SCIF_Reset(PVOID);
VOID	SCIF_GetModemStatus(PVOID, PULONG);
VOID	SCIF_PurgeComm(PVOID, DWORD);
BOOL	SCIF_XmitComChar(PVOID, UCHAR);
BOOL	SCIF_PowerOff(PVOID);
BOOL	SCIF_PowerOn(PVOID);
ULONG	SCIF_SetDCB(PVOID, LPDCB);
ULONG	SCIF_SetCommTimeouts(PVOID, LPCOMMTIMEOUTS);
BOOL	SCIF_Ioctl(PVOID, DWORD, PBYTE, DWORD, PBYTE, DWORD, PDWORD);
VOID	SCIF_GetCommProperties(PVOID, LPCOMMPROP);
BOOL	SCIF_EnableIR(PVOID, ULONG);
BOOL	SCIF_DisableIR(PVOID);
PUCHAR	Ser_InternalMapRegisterAddresses(ULONG, ULONG);
USHORT	ReadModemStatus(PVOID);
BOOL	Ser_GetRegistryData(PSCIF_INFO, LPCTSTR);

#endif // _SCIF_H_