?? x86_trans.c
字號:
m_uint64_t new_pc; /* compute the new pc */ new_pc = b->start_pc + (b->mips_trans_pos << 2); new_pc += sign_extend(offset << 2,18); /* * compare gpr[rs] and gpr[rt]. * compare the low 32 bits first (higher probability). */ x86_mov_reg_membase(b->jit_ptr,X86_EAX,X86_EDI,REG_OFFSET(rs),4); x86_alu_reg_membase(b->jit_ptr,X86_CMP,X86_EAX,X86_EDI,REG_OFFSET(rt)); test1 = b->jit_ptr; x86_branch8(b->jit_ptr, X86_CC_NE, 0, 1); x86_mov_reg_membase(b->jit_ptr,X86_EBX,X86_EDI,REG_OFFSET(rs)+4,4); x86_alu_reg_membase(b->jit_ptr,X86_CMP,X86_EBX,X86_EDI,REG_OFFSET(rt)+4); test2 = b->jit_ptr; x86_branch32(b->jit_ptr, X86_CC_E, 0, 1); x86_patch(test1,b->jit_ptr); /* insert the instruction in the delay slot */ insn_fetch_and_emit(cpu,b,1); /* set the new pc in cpu structure */ mips64_set_jump(cpu,b,new_pc,1); x86_patch(test2,b->jit_ptr); return(0);}/* BREAK */static int mips64_emit_BREAK(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ u_int code = bits(insn,6,25); x86_mov_reg_imm(b->jit_ptr,X86_EDX,code); x86_mov_reg_reg(b->jit_ptr,X86_EAX,X86_EDI,4); mips64_emit_basic_c_call(b,mips64_exec_break); insn_block_push_epilog(b); return(0);}/* CACHE */static int mips64_emit_CACHE(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int base = bits(insn,21,25); int op = bits(insn,16,20); int offset = bits(insn,0,15); mips64_emit_memop(b,MIPS_MEMOP_CACHE,base,offset,op,FALSE); return(0);}/* CFC0 */static int mips64_emit_CFC0(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int rt = bits(insn,16,20); int rd = bits(insn,11,15); mips64_emit_cp_xfr_op(b,rt,rd,cp0_exec_cfc0); return(0);}/* CTC0 */static int mips64_emit_CTC0(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int rt = bits(insn,16,20); int rd = bits(insn,11,15); mips64_emit_cp_xfr_op(b,rt,rd,cp0_exec_ctc0); return(0);}/* DADDIU */static int mips64_emit_DADDIU(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int rs = bits(insn,21,25); int rt = bits(insn,16,20); int imm = bits(insn,0,15); m_uint64_t val = sign_extend(imm,16); mips64_load_imm(b,X86_EBX,X86_EAX,val); x86_alu_reg_membase(b->jit_ptr,X86_ADD,X86_EAX,X86_EDI,REG_OFFSET(rs)); x86_alu_reg_membase(b->jit_ptr,X86_ADC,X86_EBX,X86_EDI,REG_OFFSET(rs)+4); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rt),X86_EAX,4); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rt)+4,X86_EBX,4); return(0);}/* DADDU: rd = rs + rt */static int mips64_emit_DADDU(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int rs = bits(insn,21,25); int rt = bits(insn,16,20); int rd = bits(insn,11,15); x86_mov_reg_membase(b->jit_ptr,X86_EAX,X86_EDI,REG_OFFSET(rs),4); x86_mov_reg_membase(b->jit_ptr,X86_EBX,X86_EDI,REG_OFFSET(rs)+4,4); x86_alu_reg_membase(b->jit_ptr,X86_ADD,X86_EAX,X86_EDI,REG_OFFSET(rt)); x86_alu_reg_membase(b->jit_ptr,X86_ADC,X86_EBX,X86_EDI,REG_OFFSET(rt)+4); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd),X86_EAX,4); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd)+4,X86_EBX,4); return(0);}/* DIV */static int mips64_emit_DIV(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int rs = bits(insn,21,25); int rt = bits(insn,16,20); /* eax = gpr[rs] */ x86_mov_reg_membase(b->jit_ptr,X86_EAX,X86_EDI,REG_OFFSET(rs),4); x86_cdq(b->jit_ptr); /* ebx = gpr[rt] */ x86_mov_reg_membase(b->jit_ptr,X86_EBX,X86_EDI,REG_OFFSET(rt),4); /* eax = quotient (LO), edx = remainder (HI) */ x86_div_reg(b->jit_ptr,X86_EBX,1); /* store LO */ x86_mov_reg_reg(b->jit_ptr,X86_ECX,X86_EDX,4); x86_mov_membase_reg(b->jit_ptr,X86_EDI,OFFSET(cpu_mips_t,lo),X86_EAX,4); x86_cdq(b->jit_ptr); x86_mov_membase_reg(b->jit_ptr,X86_EDI,OFFSET(cpu_mips_t,lo)+4,X86_EDX,4); /* store HI */ x86_mov_reg_reg(b->jit_ptr,X86_EAX,X86_ECX,4); x86_mov_membase_reg(b->jit_ptr,X86_EDI,OFFSET(cpu_mips_t,hi),X86_EAX,4); x86_cdq(b->jit_ptr); x86_mov_membase_reg(b->jit_ptr,X86_EDI,OFFSET(cpu_mips_t,hi)+4,X86_EDX,4); return(0);}/* DIVU */static int mips64_emit_DIVU(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int rs = bits(insn,21,25); int rt = bits(insn,16,20); /* eax = gpr[rs] */ x86_clear_reg(b->jit_ptr,X86_EDX); x86_mov_reg_membase(b->jit_ptr,X86_EAX,X86_EDI,REG_OFFSET(rs),4); /* ebx = gpr[rt] */ x86_mov_reg_membase(b->jit_ptr,X86_EBX,X86_EDI,REG_OFFSET(rt),4); /* eax = quotient (LO), edx = remainder (HI) */ x86_div_reg(b->jit_ptr,X86_EBX,0); /* store LO */ x86_mov_reg_reg(b->jit_ptr,X86_ECX,X86_EDX,4); x86_mov_membase_reg(b->jit_ptr,X86_EDI,OFFSET(cpu_mips_t,lo),X86_EAX,4); x86_cdq(b->jit_ptr); x86_mov_membase_reg(b->jit_ptr,X86_EDI,OFFSET(cpu_mips_t,lo)+4,X86_EDX,4); /* store HI */ x86_mov_reg_reg(b->jit_ptr,X86_EAX,X86_ECX,4); x86_mov_membase_reg(b->jit_ptr,X86_EDI,OFFSET(cpu_mips_t,hi),X86_EAX,4); x86_cdq(b->jit_ptr); x86_mov_membase_reg(b->jit_ptr,X86_EDI,OFFSET(cpu_mips_t,hi)+4,X86_EDX,4); return(0);}/* DMFC0 */static int mips64_emit_DMFC0(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int rt = bits(insn,16,20); int rd = bits(insn,11,15); mips64_emit_cp_xfr_op(b,rt,rd,cp0_exec_dmfc0); return(0);}/* DMFC1 */static int mips64_emit_DMFC1(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int rt = bits(insn,16,20); int rd = bits(insn,11,15); mips64_emit_cp_xfr_op(b,rt,rd,mips64_exec_dmfc1); return(0);}/* DMTC0 */static int mips64_emit_DMTC0(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int rt = bits(insn,16,20); int rd = bits(insn,11,15); mips64_emit_cp_xfr_op(b,rt,rd,cp0_exec_dmtc0); return(0);}/* DMTC1 */static int mips64_emit_DMTC1(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int rt = bits(insn,16,20); int rd = bits(insn,11,15); mips64_emit_cp_xfr_op(b,rt,rd,mips64_exec_dmtc1); return(0);}/* DSLL */static int mips64_emit_DSLL(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int rt = bits(insn,16,20); int rd = bits(insn,11,15); int sa = bits(insn,6,10); x86_mov_reg_membase(b->jit_ptr,X86_EAX,X86_EDI,REG_OFFSET(rt),4); x86_mov_reg_membase(b->jit_ptr,X86_EBX,X86_EDI,REG_OFFSET(rt)+4,4); x86_shld_reg_imm(b->jit_ptr,X86_EBX,X86_EAX,sa); x86_shift_reg_imm(b->jit_ptr,X86_SHL,X86_EAX,sa); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd),X86_EAX,4); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd)+4,X86_EBX,4); return(0);}/* DSLL32 */static int mips64_emit_DSLL32(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int rt = bits(insn,16,20); int rd = bits(insn,11,15); int sa = bits(insn,6,10); x86_mov_reg_membase(b->jit_ptr,X86_EAX,X86_EDI,REG_OFFSET(rt),4); x86_shift_reg_imm(b->jit_ptr,X86_SHL,X86_EAX,sa); x86_clear_reg(b->jit_ptr,X86_EDX); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd),X86_EDX,4); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd)+4,X86_EAX,4); return(0);}/* DSLLV */static int mips64_emit_DSLLV(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int rs = bits(insn,21,25); int rt = bits(insn,16,20); int rd = bits(insn,11,15); x86_mov_reg_membase(b->jit_ptr,X86_EAX,X86_EDI,REG_OFFSET(rt),4); x86_mov_reg_membase(b->jit_ptr,X86_EBX,X86_EDI,REG_OFFSET(rt)+4,4); x86_mov_reg_membase(b->jit_ptr,X86_ECX,X86_EDI,REG_OFFSET(rs),4); x86_alu_reg_imm(b->jit_ptr,X86_AND,X86_ECX,0x3f); x86_shld_reg(b->jit_ptr,X86_EBX,X86_EAX); x86_shift_reg(b->jit_ptr,X86_SHL,X86_EAX); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd),X86_EAX,4); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd)+4,X86_EBX,4); return(0);}/* DSRA */static int mips64_emit_DSRA(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int rt = bits(insn,16,20); int rd = bits(insn,11,15); int sa = bits(insn,6,10); x86_mov_reg_membase(b->jit_ptr,X86_EAX,X86_EDI,REG_OFFSET(rt),4); x86_mov_reg_membase(b->jit_ptr,X86_EBX,X86_EDI,REG_OFFSET(rt)+4,4); x86_shrd_reg_imm(b->jit_ptr,X86_EAX,X86_EBX,sa); x86_shift_reg_imm(b->jit_ptr,X86_SAR,X86_EBX,sa); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd),X86_EAX,4); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd)+4,X86_EBX,4); return(0);}/* DSRA32 */static int mips64_emit_DSRA32(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int rt = bits(insn,16,20); int rd = bits(insn,11,15); int sa = bits(insn,6,10); x86_mov_reg_membase(b->jit_ptr,X86_EAX,X86_EDI,REG_OFFSET(rt)+4,4); x86_shift_reg_imm(b->jit_ptr,X86_SAR,X86_EAX,sa); x86_cdq(b->jit_ptr); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd),X86_EAX,4); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd)+4,X86_EDX,4); return(0);}/* DSRAV */static int mips64_emit_DSRAV(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int rs = bits(insn,21,25); int rt = bits(insn,16,20); int rd = bits(insn,11,15); x86_mov_reg_membase(b->jit_ptr,X86_EAX,X86_EDI,REG_OFFSET(rt),4); x86_mov_reg_membase(b->jit_ptr,X86_EBX,X86_EDI,REG_OFFSET(rt)+4,4); x86_mov_reg_membase(b->jit_ptr,X86_ECX,X86_EDI,REG_OFFSET(rs),4); x86_alu_reg_imm(b->jit_ptr,X86_AND,X86_ECX,0x3f); x86_shrd_reg(b->jit_ptr,X86_EAX,X86_EBX); x86_shift_reg(b->jit_ptr,X86_SAR,X86_EBX); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd),X86_EAX,4); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd)+4,X86_EBX,4); return(0);}/* DSRL */static int mips64_emit_DSRL(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int rt = bits(insn,16,20); int rd = bits(insn,11,15); int sa = bits(insn,6,10); x86_mov_reg_membase(b->jit_ptr,X86_EAX,X86_EDI,REG_OFFSET(rt),4); x86_mov_reg_membase(b->jit_ptr,X86_EBX,X86_EDI,REG_OFFSET(rt)+4,4); x86_shrd_reg_imm(b->jit_ptr,X86_EAX,X86_EBX,sa); x86_shift_reg_imm(b->jit_ptr,X86_SHR,X86_EBX,sa); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd),X86_EAX,4); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd)+4,X86_EBX,4); return(0);}/* DSRL32 */static int mips64_emit_DSRL32(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int rt = bits(insn,16,20); int rd = bits(insn,11,15); int sa = bits(insn,6,10); x86_mov_reg_membase(b->jit_ptr,X86_EAX,X86_EDI,REG_OFFSET(rt)+4,4); x86_shift_reg_imm(b->jit_ptr,X86_SHR,X86_EAX,sa); x86_clear_reg(b->jit_ptr,X86_EDX); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd),X86_EAX,4); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd)+4,X86_EDX,4); return(0);}/* DSRLV */static int mips64_emit_DSRLV(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int rs = bits(insn,21,25); int rt = bits(insn,16,20); int rd = bits(insn,11,15); x86_mov_reg_membase(b->jit_ptr,X86_EAX,X86_EDI,REG_OFFSET(rt),4); x86_mov_reg_membase(b->jit_ptr,X86_EBX,X86_EDI,REG_OFFSET(rt)+4,4); x86_mov_reg_membase(b->jit_ptr,X86_ECX,X86_EDI,REG_OFFSET(rs),4); x86_alu_reg_imm(b->jit_ptr,X86_AND,X86_ECX,0x3f); x86_shrd_reg(b->jit_ptr,X86_EAX,X86_EBX); x86_shift_reg(b->jit_ptr,X86_SHR,X86_EBX); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd),X86_EAX,4); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd)+4,X86_EBX,4); return(0);}/* DSUBU: rd = rs - rt */static int mips64_emit_DSUBU(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ int rs = bits(insn,21,25); int rt = bits(insn,16,20); int rd = bits(insn,11,15); x86_mov_reg_membase(b->jit_ptr,X86_EAX,X86_EDI,REG_OFFSET(rs),4); x86_mov_reg_membase(b->jit_ptr,X86_EBX,X86_EDI,REG_OFFSET(rs)+4,4); x86_alu_reg_membase(b->jit_ptr,X86_SUB,X86_EAX,X86_EDI,REG_OFFSET(rt)); x86_alu_reg_membase(b->jit_ptr,X86_SBB,X86_EBX,X86_EDI,REG_OFFSET(rt)+4); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd),X86_EAX,4); x86_mov_membase_reg(b->jit_ptr,X86_EDI,REG_OFFSET(rd)+4,X86_EBX,4); return(0);}/* ERET */static int mips64_emit_ERET(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2)); x86_mov_reg_reg(b->jit_ptr,X86_EAX,X86_EDI,4); mips64_emit_basic_c_call(b,mips64_exec_eret); insn_block_push_epilog(b); return(0);}/* J (Jump) */static int mips64_emit_J(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ u_int instr_index = bits(insn,0,25); m_uint64_t new_pc; /* compute the new pc */ new_pc = b->start_pc + (b->mips_trans_pos << 2); new_pc &= ~((1 << 28) - 1); new_pc |= instr_index << 2; /* insert the instruction in the delay slot */ insn_fetch_and_emit(cpu,b,1); /* set the new pc in cpu structure */ mips64_set_jump(cpu,b,new_pc,1); return(0);}/* JAL (Jump And Link) */static int mips64_emit_JAL(cpu_mips_t *cpu,insn_block_t *b,mips_insn_t insn){ u_int instr_index = bits(insn,0,25); m_uint64_t new_pc,ret_pc;?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -