library ieee;
use ieee.std_logic_1164.all;

ENTITY sumador IS
	GENERIC(SIZE: INTEGER);
	PORT(a		:IN STD_LOGIC_VECTOR(SIZE - 1 downto 0);
  		 b		:IN	STD_LOGIC_VECTOR(SIZE - 1 downto 0);
		 cin	:IN STD_LOGIC;
		 s		:OUT STD_LOGIC_VECTOR(SIZE - 1 downto 0);
		 cout	:OUT STD_LOGIC);
END sumador;


architecture josan of sumador is

component fa 
	PORT(
			a		:IN STD_LOGIC;
			b		:IN STD_LOGIC;
			cin		:IN STD_LOGIC;
			s		:OUT STD_LOGIC;
			cout	:OUT STD_LOGIC);
END component;

signal acarreo		:STD_LOGIC_VECTOR(SIZE downto 0);

begin

 acarreo(0) <= cin;

 suma: for i in 0 to SIZE - 1 generate
	suma1bit: fa
		port map(a => a(i),
				b => b(i),
				cin => acarreo(i),
				s => s(i),
				cout => acarreo(i+1));     
   end generate;
 
 cout <= acarreo(SIZE);
end josan;