<pre>     <b>entity</b> AND_GATE <b>is</b>
         <b>generic</b> (I1toO, I2toO: DELAY_LENGTH := 4 ns);
         <b>port</b>        (I1, I2: <b>in</b> BIT;   O: <b>out</b> BIT);
     <b>end</b> <b>entity</b> AND_GATE;

     <b>entity</b> XOR_GATE <b>is</b>
         <b>generic</b> (I1toO, I2toO : DELAY_LENGTH := 4 ns);
         <b>port</b>        (I1, I2: <b>in</b> BIT;    O : <b>out</b> BIT);
     <b>end</b> <b>entity</b> XOR_GATE;

     <b>package</b> MY_GATES <b>is</b>
        <b>component</b> AND_GATE <b>is</b>
           <b>generic</b>  (I1toO, I2toO: DELAY_LENGTH := 4 ns);
           <b>port</b>       (I1, I2: <b>in</b> BIT;   O: <b>out</b> BIT);
        <b>end</b> <b>component</b> AND_GATE;

        <b>component</b> XOR_GATE <b>is</b>
           <b>generic</b>  (I1toO, I2toO: DELAY_LENGTH := 4 ns);
           <b>port</b>       (I1, I2: <b>in</b> BIT;   O : <b>out</b> BIT);
        <b>end</b> <b>component</b> XOR_GATE;
     <b>end</b> <b>package</b> MY_GATES;

     <b>entity</b> Half_Adder <b>is</b>
         <b>port</b>    (X, Y: <b>in</b> BIT;
                    Sum, Carry: <b>out</b> BIT);
     <b>end</b> <b>entity</b> Half_Adder;

     <b>use</b> WORK.MY_GATES.<b>all</b>;
     <b>architecture</b> Structure <b>of</b> Half_Adder <b>is</b>
         <b>for</b> L1: XOR_GATE <b>use</b>
             <b>entity</b> WORK.XOR_GATE(Behavior)              --  The primary binding indication
                  <b>generic</b> <b>map</b> (3 ns, 3 ns)               --  for instance L1.
                  <b>port</b> <b>map</b> (I1 => I1, I2 => I2, O => O);

         <b>for</b> L2: AND_GATE <b>use</b>
             <b>entity</b> WORK.AND_GATE(Behavior)              --  The primary binding indication
                  <b>generic</b> <b>map</b> (3 ns, 4 ns)               --  for instance L2.
                  <b>port</b> <b>map</b> (I1, <b>open</b>, O);

     <b>begin</b>
         L1: XOR_GATE    <b>port</b> <b>map</b> (X, Y, Sum);
         L2: AND_GATE    <b>port</b> <b>map</b> (X, Y, Carry);
     <b>end</b> <b>architecture</b> Structure;

     <b>use</b> WORK.GLOBAL_SIGNALS.<b>all</b>;
     <b>configuration</b> Different <b>of</b> Half_Adder <b>is</b>
         <b>for</b> Structure
              <b>for</b> L1: XOR_GATE
                   <b>generic</b> <b>map</b> (2.9 ns, 3.6 ns);         --  The  incremental binding
              <b>end</b> <b>for</b>;                                   --  indication of L1; rebinds its generics.

              <b>for</b> L2: AND_GATE
                   <b>generic</b> <b>map</b> (2.8 ns, 3.25 ns)         --  The incremental binding
                   <b>port</b> <b>map</b> (I2 => Tied_High);           --  indication L2; rebinds its generics
              <b>end</b> <b>for</b>;                                   --  and binds its open port.
        <b>end</b> <b>for</b>;
     <b>end</b> <b>configuration</b> Different;

</pre>
<h4><a name="5.2.1.1">  <a href = "1076_5.HTM#5.2.1.1"> 5.2.1.1 </a>   Entity aspect</a></h4>
<p>An entity aspect identifies a particular design entity to be associated with instances of a component.  An entity aspect may also specify that such a binding is to be deferred.
<pre>     entity_aspect ::=
           <b>entity</b> <i>entity</i>_name [ ( <i>architecture</i>_identifier) ]
        | <b>configuration</b> <i>configuration</i>_name
        | <b>open</b>
</pre>
<p>The first form of entity aspect identifies a particular entity declaration and (optionally) a corresponding architecture body.  If no architecture identifier appears, then the immediately enclosing binding indication is said to<i> imply</i> the design entity whose interface is defined by the entity declaration denoted by the entity name and whose body is defined by the default binding rules for architecture identifiers (see   <a href = "1076_5.HTM#5.2.2"> 5.2.2 </a>  ).  If an architecture identifier appears, then the immediately enclosing binding indication is said to <i>imply</i> the design entity consisting of the entity declaration denoted by the entity name together with an architecture body associated with the entity declaration; the architecture identifier defines a simple name that is used during the elaboration of a design hierarchy to select the appropriate architecture body.  In either case, the corresponding component instances are said to be <i>fully</i> <i>bound</i>.
<p>At the time of the analysis of an entity aspect of the first form, the library unit corresponding to the entity declaration denoted by the entity name is required to exist; moreover, the design unit containing the entity aspect depends on the denoted entity declaration.  If the architecture identifier is also present, the library unit corresponding to the architecture identifier is required  to exist only if the binding indication is part of a component configuration containing explicit block configurations or explicit component configurations; only in this case does the design unit containing the entity aspect also depend on the denoted architecture body.  In any case, the library unit corresponding to the architecture identifier is required to exist at the time that the design entity implied by the enclosing binding indication is bound to the component instance denoted by the component configuration or configuration specification containing the binding indication; if the library unit corresponding to the architecture identifier was required to exist during analysis, it is an error if the architecture identifier does not denote the same library unit as that denoted during analysis.  The library unit corresponding to the architecture identifier, if it exists, must be an architecture body associated with the entity declaration denoted by the entity name.
<p>The second form of entity aspect identifies a design entity indirectly by identifying a configuration.  In this case, the entity aspect is said to <i>imply</i> the design entity at the apex of the design hierarchy that is defined by the configuration denoted by the configuration name.
<p>At the time of the analysis of an entity aspect of the second form, the library unit corresponding to the configuration name is required to exist.  The design unit containing the entity aspect depends on the configuration denoted by the configuration name.
<p>The third form of entity aspect is used to specify that the identification of the design entity is to be deferred.  In this case, the immediately enclosing binding indication is said to <i>not imply</i> any design entity.  Furthermore,the immediately enclosing binding indication must not include a generic map aspect or a port map aspect.

<h4><a name="5.2.1.2">  <a href = "1076_5.HTM#5.2.1.2"> 5.2.1.2 </a>   Generic map and port map aspects</a></h4>
<p>A generic map aspect associates values with the formal generics of a block.  Similarly, a port map aspect associates signals or values with the formal ports of a block.  The following applies to both external blocks defined by design entities and to internal blocks defined by block statements.
<pre>     generic_map_aspect ::=
         <b>generic map</b> ( <i>generic</i>_association_list )

     port_map_aspect ::=
         <b>port map</b> ( <i>port</i>_association_list )
</pre>
<p>Both named and positional association are allowed in a port or generic association list.
<p>The following definitions are used in the remainder of this subclause:
<ul>
<p>--  The term <i>actual</i> refers to an actual designator that appears either in an association element of a port association list or in an association element of a generic association list.
<p>--  The term <i>formal</i> refers to a formal designator that appears either in an association element of a port association list or in an association element of a generic association list.
</ul>
<p>The purpose of port and generic map aspects is as follows:
<ul>
<p>--  Generic map aspects and port map aspects appearing immediately within a binding indication associate actuals with the formals of the design entity interface implied by the immediately enclosing binding indication.  No scalar formal may be associated with more than one actual.  No scalar subelement of any composite formal may be associated more than once in the same association list.
<p>     Each scalar subelement of every local port of the component instances to which an enclosing configuration specification or component configuration applies must be associated as an actual with at least one formal or with a scalar subelement thereof.  The actuals of these associations for a given local port may be the entire local port or any slice or subelement (or slice thereof).  The actuals in these associations must be locally static names.
<p>--  Generic map aspects and port map aspects appearing immediately within a component instantiation statement associate actuals with the formals of the component instantiated by the statement.  No scalar formal may be associated with more than one actual.  No scalar subelement of any composite formal may be associated with more than one scalar subelement of an actual.
<p>--  Generic map aspects and port map aspects appearing immediately within a block header associate actuals with the formals defined by the same block header.  No scalar formal may be associated with more than one actual.  No scalar subelement of any composite formal may be associated with more than one actual or with a scalar subelement thereof.
</ul>
<p>An actual associated with a formal generic in a generic map aspect must be an expression or the reserved word <b>open</b>; an actual associated with a formal port in a port map aspect must be a signal, an expression, or the reserved word<b> open</b>.
<p>Certain restrictions apply to the actual associated with a formal port in a port map aspect; these restrictions are described in   <a href = "1076_1.HTM#1.1.1.2"> 1.1.1.2 </a>  .
<p>A formal that is not associated with an actual is said to be an <i>unassociated</i> formal.
<p>NOTE--A generic map aspect appearing immediately within a binding indication need not associate every formal generic with an actual.  These formals may be left unbound so that, for example, a component configuration within a configuration  declaration may subsequently bind them.
<p><i>Example:</i>
<pre>     <b>entity</b> Buf <b>is</b>
         <b>generic</b> (Buf_Delay: TIME := 0 ns);
         <b>port</b> (Input_pin: <b>in</b> Bit; Output_pin: <b>out</b> Bit);
     <b>end</b> Buf;
 
     <b>architecture</b> DataFlow <b>of</b> Buf <b>is</b>
     <b>begin</b>
         Output_pin &lt;= Input_pin<b> after</b> Buf_Delay;
     <b>end</b> DataFlow;

     <b>entity</b> Test_Bench <b>is</b>
     <b>end</b> Test_Bench;

     <b>architecture</b> Structure <b>of</b> Test_Bench <b>is</b>
         <b>component</b> Buf <b>is</b>
            <b>generic</b> (Comp_Buf_Delay: TIME);