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<title>VHDL LRM- Introduction</title>
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<h1><a name="12">Section 12</a></h1>
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<h1>Elaboration and execution</h1>
<p>
<p>The process by which a declaration achieves its effect is called the <i>elaboration</i> of the declaration. After its elaboration, a declaration is said to be elaborated. Prior to the completion of its elaboration (including before the elaboration), the declaration is not yet elaborated.
<p>Elaboration is also defined for design hierarchies, declarative parts, statement parts (containing concurrent statements), and concurrent statements. Elaboration of such constructs is necessary in order ultimately to elaborate declarative items that are declared within those constructs.
<p>In order to execute a model, the design hierarchy defining the model must first be elaborated. Initialization of nets (see <a href = "1076_12.HTM#12.6.2"> 12.6.2 </a> ) in the model then occurs. Finally, simulation of the model proceeds. Simulation consists of the repetitive execution of the <i>simulation</i> <i>cycle</i>, during which processes are executed and nets updated.
<h2><a name="12.1"> <a href = "1076_12.HTM#12.1"> 12.1 </a> Elaboration of a design hierarchy</a></h2>
<p>The elaboration of a design hierarchy creates a collection of processes interconnected by nets; this collection of processes and nets can then be executed to simulate the behavior of the design.
<p>A design hierarchy may be defined by a design entity. Elaboration of a design hierarchy defined in this manner consists of the elaboration of the block statement equivalent to the external block defined by the design entity. The architecture of this design entity is assumed to contain an implicit configuration specification (see <a href = "1076_5.HTM#5.2"> 5.2 </a> ) for each component instance that is unbound in this architecture; each configuration specification has an entity aspect denoting an anonymous configuration declaration identifying the visible entity declaration (see <a href = "1076_5.HTM#5.2"> 5.2 </a> ) and supplying an implicit block configuration (see <a href = "1076_1.HTM#1.3.1"> 1.3.1 </a> ) that binds and configures a design entity identified according to the rules of <a href = "1076_5.HTM#5.2.2"> 5.2.2 </a> . The equivalent block statement is defined in <a href = "1076_9.HTM#9.6.2"> 9.6.2 </a> . Elaboration of a block statement is defined in <a href = "1076_12.HTM#12.4.1"> 12.4.1 </a> .
<p>A design hierarchy may also be defined by a configuration. Elaboration of a configuration consists of the elaboration of the block statement equivalent to the external block defined by the design entity configured by the configuration. The configuration contains an implicit component configuration(see <a href = "1076_1.HTM#1.3.2"> 1.3.2 </a> ) for each unbound component instance contained within the external block and an implicit block configuration (see <a href = "1076_1.HTM#1.3.1"> 1.3.1 </a> ) for each internal block contained within the external block.
<p>An implementation may allow, but is not required to allow, a design entity at the root of a design hierarchy to have generics and ports. If an implementation allows these <i>top-level</i> interface objects, it may restrict their allowed types and modes in an implementation-defined manner. Similarly,the means by which top-level interface objects are associated with the external environment of the hierarchy are also defined by an implementation supporting top-level interface objects.
<p>Elaboration of a block statement involves first elaborating each not-yet-elaborated package containing declarations referenced by the block. Similarly, elaboration of a given package involves first elaborating each not-yet-elaborated package containing declarations referenced by the given package. Elaboration of a package additionally consists of the
<ol type="a">
<li>Elaboration of the declarative part of the package declaration,eventually followed by<br>
<li>Elaboration of the declarative part of the corresponding package body, if the package has a corresponding package body.
</ol>
<p>Step b above, the elaboration of a package body, may be deferred until the declarative parts of other packages have been elaborated, if necessary, because of the dependencies created between packages by their interpackage references.
<p>Elaboration of a declarative part is defined in <a href = "1076_12.HTM#12.3"> 12.3 </a> .
<p><i>Examples:</i>
<pre> -- In the following example, because of the dependencies between the packages, the
-- elaboration of either package body must follow the elaboration of both package
-- declarations.
<b>package</b> P1 <b>is</b>
<b>constant</b> C1: INTEGER := 42;
<b>constant</b> C2: INTEGER;
<b>end</b> <b>package</b> P1;
<b>package</b> P2 <b>is</b>
<b>constant</b> C1: INTEGER := 17;
<b>constant</b> C2: INTEGER;
<b>end</b> <b>package</b> P2;
<b>package body</b> P1 <b>is</b>
<b>constant</b> C2: INTEGER := Work.P2.C1;
<b>end</b> <b>package</b> <b>body</b> P1;
<b>package body</b> P2 <b>is</b>
<b>constant</b> C2: INTEGER := Work.P1.C1;
<b>end</b> <b>package</b> <b>body</b> P2;
-- If a design hierarchy is described by the following design entity:
<b>entity</b> E <b>is</b> <b>end</b>;
<b>architecture</b> A <b>of</b> E <b>is</b>
<b> component</b> comp
<b>port</b> (...);
<b>end</b> <b>component</b>;
<b>begin</b>
C: comp <b>port</b> <b>map</b> (...);
B: <b>block</b>
...
<b>begin</b>
...
<b>end</b> <b>block</b> B;
<b>end</b> <b>architecture</b> A;
-- then its architecture contains the following implicit configuration specification at the
-- end of its declarative part:
<b>for</b> C: comp <b>use</b> <b>configuration</b> <i>anonymous</i>;
-- and the following configuration declaration is assumed to exist when E(A) is
-- elaborated:
<b>configuration</b> <i>anonymous</i> <b>of</b> L.E <b>is</b> -- L is the library in which E(A) is found.
<b>for</b> A -- The most recently analyzed architecture
-- of L.E.
<b>end</b> <b>for</b>;
<b>end</b> <b>configuration</b> <i>anonymous</i>;
</pre>
<h2><a name="12.2"> <a href = "1076_12.HTM#12.2"> 12.2 </a> Elaboration of a block header</a></h2>
<p>Elaboration of a block header consists of the elaboration of the generic clause, the generic map aspect, the port clause, and the port map aspect, in that order.
<h3><a name="12.2.1"> <a href = "1076_12.HTM#12.2.1"> 12.2.1 </a> The generic clause</a></h3>
<p>Elaboration of a generic clause consists of the elaboration of each of the equivalent single generic declarations contained in the clause, in the order given. The elaboration of a generic declaration consists of elaborating the subtype indication and then creating a generic constant of that subtype.
<p>The value of a generic constant is not defined until a subsequent generic map aspect is evaluated or, in the absence of a generic map aspect, until the default expression associated with the generic constant is evaluated to determine the value of the constant.
<h3><a name="12.2.2"> <a href = "1076_12.HTM#12.2.2"> 12.2.2 </a> The generic map aspect</a></h3>
<p>Elaboration of a generic map aspect consists of elaborating the generic association list. The generic association list contains an implicit association element for each generic constant that is not explicitly associated with an actual or that is associated with the reserved word <b>open</b>; the actual part of such an implicit association element is the default expression appearing in the declaration of that generic constant.
<p>Elaboration of a generic association list consists of the elaboration of each generic association element in the association list. Elaboration of a generic association element consists of the elaboration of the formal part and the evaluation of the actual part. The generic constant or subelement or slice thereof designated by the formal part is then initialized with the value resulting from the evaluation of the corresponding actual part. It is an error if the value of the actual does not belong to the subtype denoted by the subtype indication of the formal. If the subtype denoted by the subtype indication of the declaration of the formal is a constrained array subtype,then an implicit subtype conversion is performed prior to this check. It is also an error if the type of the formal is an array type and the value of each element of the actual does not belong to the element subtype of the formal.
<h3><a name="12.2.3"> <a href = "1076_12.HTM#12.2.3"> 12.2.3 </a> The port clause</a></h3>
<p>Elaboration of a port clause consists of the elaboration of each of the equivalent single port declarations contained in the clause, in the order given. The elaboration of a port declaration consists of elaborating the subtype indication and then creating a port of that subtype.
<h3><a name="12.2.4"> <a href = "1076_12.HTM#12.2.4"> 12.2.4 </a> The port map aspect</a></h3>
<p>Elaboration of a port map aspect consists of elaborating the port association list.
<p>Elaboration of a port association list consists of the elaboration of each port association element in the association list whose actual is not the reserved word <b>open</b>. Elaboration of a port association element consists of the elaboration of the formal part; the port or subelement or slice thereof designated by the formal part is then associated with the signal or expression designated by the actual part. This association involves a check that the restrictions on port associations (see <a href = "1076_1.HTM#1.1.1.2"> 1.1.1.2 </a> ) are met. It is an error if this check fails.
<p>If a given port is a port of mode <b>in</b> whose declaration includes a default expression, and if no association element associates a signal or expression with that port, then the default expression is evaluated and the effective and driving value of the port is set to the value of the default expression. Similarly, if a given port of mode <b>in</b> is associated with an expression, that expression is evaluated and the effective and driving value of the port is set to the value of the expression. In the event that the value of a port is derived from an expression in either fashion, references to the predefined attributes 'DELAYED, 'STABLE, 'QUIET, 'EVENT, 'ACTIVE, 'LAST_EVENT,'LAST_ACTIVE, 'LAST_VALUE, 'DRIVING, and 'DRIVING_VALUE of the port return values indicating that the port has the given driving value with no activity at any time (see <a href = "1076_12.HTM#12.6.3"> 12.6.3 </a> ).
<p>If an actual signal is associated with a port of any mode, and if the type of the formal is a scalar type, then it is an error if (after applying any conversion function or type conversion expression present in the actual part) the bounds and direction of the subtype denoted by the subtype indication of the formal are not identical to the bounds and direction of the subtype denoted by the subtype indication of the actual. If an actual expression is associated with a formal port (of mode <b>in</b>), and if the type of the formal is a scalar type, then it is an error if the value of the expression does not belong to the subtype denoted by the subtype indication of the declaration of the formal.
<p>If an actual signal or expression is associated with a formal port, and if the formal is of a constrained array subtype, then it is an error if the actual does not contain a matching element for each element of the formal. In the case of an actual signal, this check is made after applying any conversion function or type conversion that is present in the actual part. If an actual signal or expression is associated with a formal port, and if the subtype denoted by the subtype indication of the declaration of the formal is an unconstrained array type, then the subtype of the formal is taken from the actual associated with that formal. It is also an error if the mode of the formal is <b>in</b> or <b>inout</b> and the value of each element of the actual array (after applying any conversion function or type conversion present in the actual part) does not belong to the element subtype of the formal. If the formal port is of mode <b>out</b>, <b>inout</b>, or <b>buffer</b>, it is also an error if the value of each element of the formal(after applying any conversion function or type conversion present in the formal part) does not belong to the element subtype of the actual.
<p>If an actual signal or expression is associated with a formal port, and if the formal is of a record subtype, then it is an error if the rules of the preceding three paragraphs do not apply to each element of the record subtype. In the case of an actual signal, these checks are made after applying any conversion function or type conversion that is present in the actual part.
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