<b>when</b> choice_list2 =>
             wave_transform2
                &#183
                &#183
                &#183
          <b>when</b> choice_listN-1 =>
             wave_transformN-1
          <b>when</b> choice_listN =>
             wave_transformN
     <b>end case</b>;
</pre>
<p>Wave transforms are defined in   <a href = "1076_9.HTM#9.5.1"> 9.5.1 </a>  .
<p>The characteristics of the select expression, the waveforms, and the choices in the selected assignment statement must be such that the case statement in the equivalent process statement is a legal statement.
<h2><a name="9.6">  <a href = "1076_9.HTM#9.6"> 9.6 </a>   Component instantiation statements</a></h2>
<p>A component instantiation statement defines a subcomponent of the design entity in which it appears,  associates signals or values with the ports of that subcomponent, and associates values with generics of that subcomponent.  This subcomponent is one instance of a class of components defined by a corresponding component declaration, design entity, or configuration declaration.
<pre>     component_instantiation_statement ::=
        <i>instantiation</i>_label :
             instantiated_unit
                  [ generic_map_aspect ]
                  [ port_map_aspect ] ;

     instantiated_unit ::=
          [ <b>component</b> ] <i>component</i>_name
          | <b>entity</b> <i>entity</i>_name [ ( <i>architecture</i>_identifier ) ]
          | <b>configuration</b> <i>configuration</i>_name
</pre>
<p>The component name, if present, must be the name of a component declared in a component declaration.  The entity name, if present, must be the name of a previously analyzed entity interface; if an architecture identifier appears in the instantiated unit, then that identifier must be the same as the simple name of an architecture body associated with the entity declaration denoted by the corresponding entity name.  The architecture identifier defines a simple name that is used during the elaboration of a design hierarchy to select the appropriate architecture body.  The configuration name, if present, must be the name of a previously analyzed configuration declaration.  The generic map aspect, if present, optionally associates a single actual with each local generic (or member)  in the corresponding component declaration or entity interface.  Each local generic member must be associated at most once.  Similarly, the port map aspect, if present, optionally associates a single actual with each local port member in the corresponding component declaration or entity interface.  Each local port member must be associated at most once.  The generic map and port map aspects are described in   <a href = "1076_5.HTM#5.2.1.2"> 5.2.1.2 </a>  .
<p>If an instantiated unit containing the reserved word <b>entity</b> does not contain an explicitly specified architecture identifier, then the architecture identifier is implicitly specified according to the rules given in   <a href = "1076_5.HTM#5.2.2"> 5.2.2 </a>  .  The architecture identifier defines a simple name that is used during the elaboration of a design hierarchy to select the appropriate architecture body.
<p>A component instantiation statement and a corresponding configuration specification, if any, taken together, imply that the block hierarchy within the design entity containing the component instantiation is to be extended with a unique copy of the block defined by another design entity.  The generic map and port map aspects in the component instantiation statement and in the binding indication of the configuration specification identify the connections that are to be made in order to accomplish the extension.

<h4>NOTES</h4>
<p>1--A configuration specification can be used to bind a particular instance of a component to a design entity and to associate the local generics and local ports of the component with the formal generics and formal ports of that design entity.  A configuration specification may apply to a component instantiation statement only if the name in the instantiated unit of the component instantiation statement denotes a component declaration.  (See   <a href = "1076_5.HTM#5.2"> 5.2 </a>  .)
<p>2--The component instantiation statement may be used to imply a structural organization for a hardware design.  By using component declarations, signals,and component instantiation statements, a given (internal or external) block may be described in terms of subcomponents that are interconnected by signals.
<p>3--Component instantiation provides a way of structuring the logical decomposition of a design.  The precise structural or behavioral characteristics of a given subcomponent may be described later, provided that the instantiated unit is a component declaration.  Component instantiation also provides a mechanism for reusing existing designs in a design library.  A configuration specification can bind a given component instance to an existing design entity, even if the generics and ports of the entity declaration do not precisely match those of the component (provided that the instantiated unit is a component declaration); if the generics or ports of the entity declaration do not match those of the component, the configuration specification must contain a generic map or port map, as appropriate, to map the generics and ports of the entity declaration to those of the component.
<h3><a name="9.6.1">  <a href = "1076_9.HTM#9.6.1"> 9.6.1 </a>   Instantiation of a component</a></h3>
<p>A component instantiation statement whose instantiated unit contains a name denoting a component is equivalent to a pair of nested block statements that couple the block hierarchy in the containing design unit to a unique copy of the block hierarchy contained in another design unit (i.e., the subcomponent).The outer block represents the component declaration; the inner block represents the design entity to which the component is bound.  Each is defined by a block statement.
<p>The header of the block statement corresponding to the component declaration consists of the generic and port clauses (if present) that appear in the component declaration, followed by the generic map and port map aspects (if present) that appear in the corresponding component instantiation statement.  The meaning of any identifier appearing in the header of this block statement is associated with the corresponding occurrence of the identifier in the generic clause, port clause, generic map aspect, or port map aspect,respectively.  The statement part of the block statement corresponding to the component declaration consists of a nested block statement corresponding to the design entity.
<p>The header of the block statement corresponding to the design entity consists of the generic and port clauses (if present) that appear in the entity declaration that defines the interface to the design entity, followed by the generic map and port map aspects (if present) that appear in the binding indication that binds the component instance to that design entity.  The declarative part of the block statement corresponding to the design entity consists of the declarative items from the entity declarative part, followed by the declarative items from the declarative part of the corresponding architecture body.  The statement part of the block statement corresponding to the design entity consists of the concurrent statements from the entity statement part, followed by the concurrent statements from the statement part of the corresponding architecture body.  The meaning of any identifier appearing anywhere in this block statement is that associated with the corresponding occurrence of the identifier in the entity declaration or architecture body, respectively.
<p>For example, consider the following component declaration, instantiation, and corresponding configuration specification:
<pre>     <b>component</b>
        COMP <b>port</b> (A,B : <b>inout </b>BIT);
     <b>end component</b>;

     <b>for </b>C: COMP <b>use</b>
          <b>entity</b> X(Y)
          <b>port map</b> (P1 => A, P2 => B) ;
                 &#183
                 &#183
                 &#183
     C:  COMP <b>port map</b> (A => S1, B => S2);
</pre>
<p>Given the following entity declaration and architecture declaration:
<pre>     <b>entity</b> X <b>is</b>
          <b>port</b> (P1, P2 : <b>inout </b>BIT);
          <b>constant</b> Delay: Time := 1 ms;
     <b>begin</b>
         CheckTiming (P1, P2, 2*Delay);
     <b>end</b> X ;

     <b>architecture</b> Y <b>of</b> X <b>is</b>
          <b>signal</b> P3: Bit;
     <b>begin</b>
         P3 &lt;= P1 <b>after</b> Delay;
         P2 &lt;= P3 <b>after</b> Delay;
         B:  <b>block</b>
                 &#183
                 &#183
                 &#183
             <b>begin</b>
                 &#183
                 &#183
                 &#183
             <b>end block</b>;
     <b>end</b> Y;
</pre>
<p>then the following block statements implement the coupling between the block hierarchy in which component instantiation statement C appears and the block hierarchy contained in design entity X(Y):
<pre>     C: <b>block                                                </b>--  Component block.
             <b>port</b> (A,B : <b>inout </b>BIT);                         --  Local ports.
             <b>port map</b> (A => S1, B => S2);                    --  Actual/local binding.
         <b>begin</b>
             X:  <b>block                                 </b>      --  Design entity block.
                    <b>port</b> (P1, P2 : <b>inout </b>BIT);               --  Formal ports.
                    <b>port map</b> (P1 => A, P2 => B);             --  Local/formal binding.
                    <b>constant</b> Delay: Time := 1 ms;            --  Entity declarative item.
                    <b>signal</b> P3: Bit;                          --  Architecture declarative item.
<b>                 begin</b>
               CheckTiming (P1, P2, 2*Delay);                --  Entity statement.
               P3 &lt;= P1 <b>after</b> Delay;                         --  Architecture statements.
               P2 &lt;= P3 <b>after</b> Delay;
               B:  <b>block                                     </b>--  Internal block hierarchy.
                      &#183
                      &#183
                      &#183
               <b>begin</b>
                      &#183
                      &#183
                      &#183
                  <b>  end block</b>;
<b>               end block</b> X ;
     <b>end block </b>C;
</pre>
<p>The block hierarchy extensions implied by component instantiation statements that are bound to design entities are accomplished during the elaboration of a design hierarchy (see Section 12).
<h3><a name="9.6.2">  <a href = "1076_9.HTM#9.6.2"> 9.6.2 </a>   Instantiation of a design entity</a></h3>
<p>A component instantiation statement whose instantiated unit denotes either a design entity or a configuration declaration is equivalent to a pair of nested block statements that couple the block hierarchy in the containing design unit to a unique copy of the block hierarchy contained in another design unit (i.e.,the subcomponent).  The outer block represents the component instantiation statement; the inner block represents the design entity to which the instance is bound.  Each is defined by a block statement.
<p>The header of the block statement corresponding to the component instantiation statement is empty, as is the declarative part of this block statement.  The statement part of the block statement corresponding to the component declaration consists of a nested block statement corresponding to the design entity.
<p>The header of the block statement corresponding to the design entity consists of the generic and port clauses (if present) that appear in the entity declaration that defines the interface to the design entity, followed by the generic map and port map aspects (if present) that appear in the component instantiation statement that binds the component instance to a copy of that design entity.  The declarative part of the block statement corresponding to the design entity consists of the declarative items from the entity declarative part, followed by the declarative items from the declarative part of the corresponding architecture body.  The statement part of the block statement corresponding to the design entity consists of the concurrent statements from the entity statement part, followed by the concurrent statements from the statement part of the corresponding architecture body.  The meaning of any identifier appearing anywhere in this block statement is that associated with the corresponding occurrence of the identifier in the entity declaration or architecture body, respectively.
<p>For example, consider the following design entity:
<pre>     <b>entity</b> X <b>is</b>
          <b>port</b> (P1, P2: <b>inout</b> BIT);
          <b>constant</b> Delay: DELAY_LENGTH:= 1 ms;
          <b>use</b> WORK.TimingChecks.<b>all</b>;
     <b>begin</b>
<b>          </b>CheckTiming(P1, P2, 2*Delay);
     <b>end</b> <b>entity</b> X;

     <b>architecture</b> Y<b> of</b> X <b>is</b>
          <b>signal</b> P3: BIT;
     <b>begin</b>
          P3 &lt;= P1 <b>after</b> Delay;
          P2 &lt;= P3 <b>after</b> Delay;
          B: <b>block</b>
              &#183
              &#183
              &#183
          <b>begin</b>
              &#183
              &#183
              &#183
          <b>end</b> <b>block</b> B;
     <b>end</b> <b>architecture</b> Y;
</pre>
<p>This design entity is instantiated by the following component instantiation statement:
<pre>     C: <b>entity</b> Work.X (Y) <b>port</b> <b>map</b> (P1 => S1, P2 => S2);
</pre>
<p>The following block statements implement the coupling between the block hierarchy in which component instantiation statement C appears and the block hierarchy contained in design entity X(Y):