<pre>     C: <b>block</b>                                                --  Instance block.
     <b>begin</b>
<b></b>         X: <b>block</b>                                            --  Design entity block.
             <b>port</b> (P1, P2: <b>inout</b> BIT);                       --  Entity interface ports.
             <b>port</b> <b>map</b> (P1 => S1, P2 => S2);                  --  Instantiation statement port map.
             <b>constant</b> Delay: DELAY_LENGTH := 1 ms;           --  Entity declarative items.
             <b>use</b> WORK.TimingChecks.<b>all</b>;
             <b>signal</b> P3: BIT;                                 --  Architecture declarative item.
         <b>begin</b>
<b>            </b>CheckTiming (P1, P2, 2*Delay);                   --  Entity statement.
            P3 &lt;= P1 <b>after</b> Delay;                            --  Architecture statements.
            P2 &lt;= P3 <b>after</b> Delay;
            B: <b>block</b>
                &#183
                &#183
                &#183
            <b>begin</b>
                &#183
                &#183
                &#183
            <b>end</b> <b>block</b> B;
         <b>end block</b> X;
     <b>end block</b> C;
</pre>
<p>Moreover,consider the following design entity, which is followed by an associated configuration declaration and component instantiation:
<pre>     <b>entity</b> X <b>is</b>
          <b>port</b> (P1, P2: <b>inout</b> BIT);
          <b>constant</b> Delay: DELAY_LENGTH := 1 ms;
          <b>use</b> WORK.TimingChecks.<b>all</b>;
     <b>begin</b>
          CheckTiming (P1, P2, 2*Delay);
     <b>end</b> <b>entity</b> X;

     <b>architecture</b> Y<b> of</b> X <b>is</b>
          <b>signal</b> P3: BIT;
     <b>begin</b>
          P3 &lt;= P1 <b>after</b> Delay;
          P2 &lt;= P3 <b>after</b> Delay;
          B: <b>block</b>
              &#183
              &#183
              &#183
          <b>begin</b>
              &#183
              &#183
              &#183
          <b>end</b> <b>block</b> B;
     <b>end</b> <b>architecture</b> Y;
</pre>
<p>The configuration declaration is
<pre>     <b>configuration</b> Alpha <b>of</b> X <b>is</b>
         <b>for</b> Y
             &#183
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             &#183
         <b>end</b> <b>for</b>;
     <b>end</b> <b>configuration</b> Alpha;
</pre>
<p>The component instantiation is
<pre>     C: <b>configuration</b> Work.Alpha <b>port</b> <b>map</b> (P1 => S1, P2 => S2);
</pre>
<p>The following block statements implement the coupling between the block hierarchy in which component instantiation statement C appears and the block hierarchy contained in design entity X(Y):
<pre>     C: <b>block</b>                                                 --  Instance block.
     <b>begin</b>
         X: <b>block</b>                                             --  Design entity block.
             <b>port</b> (P1, P2: <b>inout</b> BIT);                        --  Entity interface ports.
             <b>port</b> <b>map</b> (P1 => S1, P2 => S2);                   --  Instantiation statement port map.
             <b>constant</b> Delay: DELAY_LENGTH := 1 ms;            --  Entity declarative items.
             <b>use</b> WORK.TimingChecks.<b>all</b>;
             <b>signal</b> P3: BIT;                                  --  Architecture declarative item.
         <b>begin</b>
            CheckTiming (P1, P2, 2*Delay);                    --  Entity statement.
            P3 &lt;= P1 <b>after</b> Delay;                             --  Architecture statements.
            P2 &lt;= P3 <b>after</b> Delay;
            B: <b>block</b>
                &#183
                &#183
                &#183
            <b>begin</b>
                &#183
                &#183
                &#183
            <b>end</b> <b>block</b> B;
         <b>end block</b> X;
     <b>end block</b> C;
</pre>
<p>The block hierarchy extensions implied by component instantiation statements that are bound to design entities occur during the elaboration of a design hierarchy(see Section 12).
<h2><a name="9.7">  <a href = "1076_9.HTM#9.7"> 9.7 </a>   Generate statements</a></h2>
<p>A generate statement provides a mechanism for iterative or conditional elaboration of a portion of a description.
<pre>     generate_statement ::=
         <i>generate</i>_label :
             generation_scheme <b>generate</b>
                 [ { block_declarative_item }
             <b>begin</b> ]
                 { concurrent_statement }
             <b>end generate</b> [ <i>generate</i>_label ] ;

     generation_scheme ::=
          <b>for</b> <i>generate</i>_parameter_specification
       | <b>if</b> condition

     label ::=  identifier
</pre>
<p>If a label appears at the end of a generate statement, it must repeat the generate label.
<p>For a generate statement with a <b>for</b> generation scheme, the generate parameter specification is the declaration of the <i>generate parameter</i> with the given identifier.  The generate parameter is a constant object whose type is the base type of the discrete range of the generate parameter specification.
<p>The discrete range in a generation scheme of the first form must be a static discrete range; similarly, the condition in a generation scheme of the second form must be a static expression.
<p>The elaboration of a generate statement is described in   <a href = "1076_12.HTM#12.4.2"> 12.4.2 </a>  .
<p><i>Example:</i>
<pre>     Gen: <b>block</b>
<b>        begin</b>
            L1: CELL <b>port map</b> (Top, Bottom, A(0), B(0)) ;

            L2: <b>for</b> I <b>in</b> 1 <b>to</b> 3 <b>generate</b>
                L3: <b>for</b> J <b>in</b> 1 <b>to</b> 3 <b>generate</b>
                    L4: <b>if</b> I+J>4 <b>generate</b>
                        L5: CELL <b>port map</b> (A(I-1),B(J-1),A(I),B(J)) ;
                    <b>end generate</b> ;
<b>                end generate</b> ;
<b>            end generate</b> ;
<b>            </b>L6: <b>for</b> I <b>in</b> 1 <b>to</b> 3 <b>generate</b>
                L7: <b>for</b> J <b>in</b> 1 <b>to</b> 3 <b>generate</b>
                    L8: <b>if</b> I+J&lt;4 <b>generate</b>
                        L9: CELL <b>port map</b> (A(I+1),B(J+1),A(I),B(J)) ;
                    <b>end generate</b> ;
<b>                end generate</b> ;
<b>            end generate</b> ;
<b>        end</b> <b>block</b> Gen;
</pre>
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