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<h1><a name="1">Section 1</a></h1>
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<h1>Design entites and configurations</h1>
<p>
<p>The <i>design entity</i> is the primary hardware abstraction in VHDL. It represents a portion of a hardware design that has well-defined inputs and outputs and performs a well-defined function. A design entity may represent an entire system, a subsystem, a board, a chip, a macro-cell, a logic gate, or any level of abstraction in between. A <i>configuration</i> can be used to describe how design entities are put together to form a complete design.
<p>A design entity may be described in terms of a hierarchy of <i>blocks</i>, each of which represents a portion of the whole design. The top-level block in such a hierarchy is the design entity itself; such a block is an <i>external</i> block that resides in a library and may be used as a component of other designs. Nested blocks in the hierarchy are <i>internal</i> blocks, defined by block statements (see <a href = "1076_9.HTM#9.1"> 9.1 </a> ).
<p>A design entity may also be described in terms of interconnected components. Each component of a design entity may be bound to a lower-level design entity in order to define the structure or behavior of that component. Successive decomposition of a design entity into components, and binding those components to other design entities that may be decomposed in like manner, results in a hierarchy of design entities representing a complete design. Such a collection of design entities is called a <i>design hierarchy</i>. The bindings necessary to identify a design hierarchy can be specified in a configuration of the top-level entity in the hierarchy.
<p>This section describes the way in which design entities and configurations are defined. A design entity is defined by an <i>entity declaration</i> together with a corresponding <i>architecture body</i>. A configuration is defined by a<i> configuration declaration</i>.
<h2><a name="1.1"> <a href = "1076_1.HTM#1.1"> 1.1 </a> Entity declarations</a></h2>
<p>An entity declaration defines the interface between a given design entity and the environment in which it is used. It may also specify declarations and statements that are part of the design entity. A given entity declaration maybe shared by many design entities, each of which has a different architecture. Thus, an entity declaration can potentially represent a class of design entities, each with the same interface.
<pre> entity_declaration ::=
<b> entity</b> identifier <b>is</b>
entity_header
entity_declarative_part
[ <b>begin</b>
entity_statement_part ]
<b>end</b> [ <b>entity</b> ] [ <i>entity</i>_simple_name ] ;
</pre>
<p>The entity header and entity declarative part consist of declarative items that pertain to each design entity whose interface is defined by the entity declaration. The entity statement part, if present, consists of concurrent statements that are present in each such design entity.
<p>If a simple name appears at the end of an entity declaration, it must repeat the identifier of the entity declaration.
<h3><a name="1.1.1"> <a href = "1076_1.HTM#1.1.1"> 1.1.1 </a> Entity header</a></h3>
<p>The entity header declares objects used for communication between a design entity and its environment.
<pre> entity_header ::=
[ <i>formal</i>_generic_clause ]
[ <i>formal</i>_port_clause ]
generic_clause ::=
<b>generic</b> ( generic_list ) ;
port_clause ::=
<b>port</b> ( port_list ) ;
</pre>
<p>The generic list in the formal generic clause defines generic constants whose values may be determined by the environment. The port list in the formal port clause defines the input and output ports of the design entity.
<p>In certain circumstances, the names of generic constants and ports declared in the entity header become visible outside of the design entity (see <a href = "1076_10.HTM#10.2"> 10.2 </a> and <a href = "1076_10.HTM#10.3"> 10.3 </a> ).
<p><i>Examples:</i>
<pre>--An entity declaration with port declarations only:
<b>entity</b> Full_Adder <b>is</b>
<b>port</b> (X, Y, Cin: <b>in</b> Bit; Cout, Sum: <b>out</b> Bit) ;
<b>end</b> Full_Adder ;
--An entity declaration with generic declarations also:
<b>entity</b> AndGate <b>is</b>
<b>generic</b>
(N: Natural := 2);
<b>port</b>
(Inputs: <b>in</b> Bit_Vector (1 <b>to</b> N);
Result: <b>out</b> Bit) ;
<b>end entity</b> AndGate ;
--An entity declaration with neither:
<b>entity</b> TestBench <b>is</b>
<b>end</b> TestBench ;
</pre>
<h4><a name="1.1.1.1"> <a href = "1076_1.HTM#1.1.1.1"> 1.1.1.1 </a> Generics</a></h4>
<p>Generics provide a channel for static information to be communicated to a block from its environment. The following applies to both external blocks defined by design entities and to internal blocks defined by block statements.
<pre> generic_list ::= <i>generic</i>_interface_list
</pre>
<p>The generics of a block are defined by a generic interface list; interface lists are described in <a href = "1076_4.HTM#4.3.2.1"> 4.3.2.1 </a> . Each interface element in such a generic interface list declares a formal generic.
<p>The value of a generic constant may be specified by the corresponding actual in a generic association list. If no such actual is specified for a given formal generic (either because the formal generic is unassociated or because the actual is <b>open</b>), and if a default expression is specified for that generic, the value of this expression is the value of the generic. It is an error if no actual is specified for a given formal generic and no default expression is present in the corresponding interface element. It is an error if some of the subelements of a composite formal generic are connected and others are either unconnected or unassociated.
<p>NOTE--Generics may be used to control structural, dataflow, or behavioral characteristics of a block, or may simply be used as documentation. In particular, generics may be used to specify the size of ports; the number of subcomponents within a block; the timing characteristics of a block; or even the physical characteristics of a design such as temperature, capacitance,location, etc.
<h4><a name="1.1.1.2"> <a href = "1076_1.HTM#1.1.1.2"> 1.1.1.2 </a> Ports</a></h4>
<p>Ports provide channels for dynamic communication between a block and its environment. The following applies to both external blocks defined by design entities and to internal blocks defined by block statements, including those equivalent to component instantiation statements and generate statements (see <a href = "1076_9.HTM#9.7"> 9.7 </a> ).
<pre> port_list ::= <i>port</i>_interface_list
</pre>
<p>The ports of a block are defined by a port interface list; interface lists are described in <a href = "1076_4.HTM#4.3.2.1"> 4.3.2.1 </a> . Each interface element in the port interface list declares a formal port.
<p>To communicate with other blocks, the ports of a block can be associated with signals in the environment in which the block is used. Moreover, the ports of a block may be associated with an expression in order to provide these ports with constant driving values; such ports must be of mode <b>in</b>. A port is itself a signal (see <a href = "1076_4.HTM#4.3.1.2"> 4.3.1.2 </a> ); thus, a formal port of a block may be associated as an actual with a formal port of an inner block. The port, signal, or expression associated with a given formal port is called the <i>actual</i> corresponding to the formal port (see <a href = "1076_4.HTM#4.3.2.2"> 4.3.2.2 </a> ). The actual, if a port or signal, must be denoted by a static name (see <a href = "1076_6.HTM#6.1"> 6.1 </a> ). The actual, if an expression, must be a globally static expression (see <a href = "1076_7.HTM#7.4"> 7.4 </a> ).
<p>After a given description is completely elaborated (see Section 12), if a formal port is associated with an actual that is itself a port, then the following restrictions apply depending upon the mode (see <a href = "1076_4.HTM#4.3.2"> 4.3.2 </a> ) of the formal port:
<ol type="a">
<li>For a formal port of mode <b>in</b>,<code>
</code>the associated actual may only be a port of mode <b>in</b>, <b>inout</b>,or <b>buffer</b>.
<p>
<li>For a formal port of mode <b>out</b>,<code>
</code>the associated actual may only be a port of mode <b>out</b> or <b>inout</b>.
<p>
<li>For a formal port of mode <b>inout</b>,<code>
</code>the associated actual may only be a port of mode <b>inout</b>.
<p>
<li>For a formal port of mode <b>buffer</b>,<code>
</code>the associated actual may only be a port of mode <b>buffer</b>.
<p>
<li>For a formal port of mode <b>linkage</b>,<code>
</code>the associated actual may be a port of any mode.
</ol>
<p>A <b>buffer</b> port may have at most one source (see <a href = "1076_4.HTM#4.3.1.2"> 4.3.1.2 </a> and <a href = "1076_4.HTM#4.3.2"> 4.3.2 </a> ).Furthermore, after a description is completely elaborated (see Section 12), any actual associated with a formal buffer port may have at most one source.
<p>If a formal port is associated with an actual port, signal, or expression, then the formal port is said to be <i>connected</i>. If a formal port is instead associated with the reserved word <b>open</b>, then the formal is said to be<i> unconnected</i>. A port of mode <b>in</b> may be unconnected or unassociated (see <a href = "1076_4.HTM#4.3.2.2"> 4.3.2.2 </a> ) only if its declaration includes a default expression (see <a href = "1076_4.HTM#4.3.2"> 4.3.2 </a> ). A port of any mode other than <b>in</b> may be unconnected or unassociated as long as its type is not an unconstrained array type. It is an error if some of the subelements of a composite formal port are connected and others are either unconnected or unassociated.
<h3><a name="1.1.2"> <a href = "1076_1.HTM#1.1.2"> 1.1.2 </a> Entity declarative part</a></h3>
<p>The entity declarative part of a given entity declaration declares items that are common to all design entities whose interfaces are defined by the given entity declaration.
<pre> entity_declarative_part ::=
{ entity_declarative_item }
entity_declarative_item ::=
subprogram_declaration
| subprogram_body
| type_declaration
| subtype_declaration
| constant_declaration
| signal_declaration
| <i>shared</i>_variable_declaration
| file_declaration
| alias_declaration
| attribute_declaration
| attribute_specification
| disconnection_specification
| use_clause
| group_template_declaration
| group_declaration
</pre>
<p>Names declared by declarative items in the entity declarative part of a given entity declaration are visible within the bodies of corresponding design entities, as well as within certain portions of a corresponding configuration declaration.
<p><i>Example:</i>
<pre>--An entity declaration with entity declarative items:
<b>entity</b> ROM <b>is</b>
<b> </b> <b>port</b> ( Addr: <b>in</b> Word;
Data: <b>out</b> Word;
Sel: <b>in</b> Bit);
<b>type</b> Instruction <b>is</b> <b>array</b> (1 <b>to</b> 5) <b>of</b> Natural;
<b>type</b> Program <b>is</b> <b>array</b> (Natural <b>range</b> <>) <b>of</b> Instruction;
<b>use</b> Work.OpCodes.<b>all</b>, Work.RegisterNames.<b>all</b>;
<b>constant</b> ROM_Code: Program :=
(
</pre>
<pre> (STM, R14, R12, 12, R13) ,
(LD, R7, 32, 0, R1 ) ,
(BAL, R14, 0, 0, R7 ) ,
·
· -- etc.
·
);
<b> end</b> ROM;
</pre>
<p>NOTE--The entity declarative part of a design entity whose corresponding architecture is decorated with the 'FOREIGN attribute is subject to special elaboration rules. See <a href = "1076_12.HTM#12.3"> 12.3 </a> .
<h3><a name="1.1.3"> <a href = "1076_1.HTM#1.1.3"> 1.1.3 </a> Entity statement part</a></h3>
<h3></h3>
<p>The entity statement part contains concurrent statements that are common to each design entity with this interface.
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