library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.lpm_components.all;

entity process_avg is
	port(clk     : in std_logic;
		 dff_clk :in std_logic;
		 dff_clr : in std_logic;--high level reset
		 datain  : in std_logic_vector(31 downto 0);
		 result  : out std_logic_vector(31 downto 0)
			);
end process_avg;

architecture behave of process_avg is

component float_add port(clk:in std_logic;
						 f_a:in std_logic_vector(31 downto 0);
						 f_b:in std_logic_vector(31 downto 0);
						 f_out:out std_logic_vector(31 downto 0)
							);
end component;

signal ff_result:std_logic_vector(31 downto 0):=(others => '0');
signal tmp_result:std_logic_vector(31 downto 0):=(others => '0');
begin
	ADD:float_add port map(clk => clk,
						   f_a => datain,
						   f_b => ff_result,
						   f_out => tmp_result
							);
							
	REG:lpm_ff generic map(LPM_WIDTH => 32)
			   port map(data => tmp_result,
						clock => dff_clk,
						aclr => dff_clr,
						Q => ff_result
						);
						
	result <= tmp_result;
						
end behave;