?? led_one.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
entity led_one is
port(clk :in std_logic;
rst_n :in std_logic;
show :in std_logic_vector (3 downto 0);
led_data :out std_logic_vector (7 downto 0)
);
end led_one;
architecture behave of led_one is
begin
process(clk,rst_n,show)
begin
if rst_n='0' then led_data <= "11000000";
elsif clk'event and clk='1' then
case show is
when "0000" => led_data <= "11000000";
when "0001" => led_data <= "11111001";
when "0010" => led_data <= "10100100";
when "0011" => led_data <= "10110000";
when "0100" => led_data <= "10011001";
when "0101" => led_data <= "10010010";
when "0110" => led_data <= "10000010";
when "0111" => led_data <= "11111000";
when "1000" => led_data <= "10000000";
when "1001" => led_data <= "10011000";
when "1010" => led_data <= "10001000";
when "1011" => led_data <= "10000011";
when "1100" => led_data <= "11000110";
when "1101" => led_data <= "10100001";
when "1110" => led_data <= "10000110";
when "1111" => led_data <= "10001110";
when others => led_data <= "11000000";
end case;
end if;
end process;
end behave;
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