{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 27 15:44:31 2009 " "Info: Processing started: Fri Feb 27 15:44:31 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off c_a -c c_a --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off c_a -c c_a --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 2 -1 0 } } { "d:/alter/quartusii/win/Assignment Editor.qase" "" { Assignment "d:/alter/quartusii/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register Q1\[9\]~reg0 c_a~reg0 422.12 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 422.12 MHz between source register \"Q1\[9\]~reg0\" and destination register \"c_a~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.261 ns + Longest register register " "Info: + Longest register to register delay is 1.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q1\[9\]~reg0 1 REG LC_X52_Y7_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y7_N7; Fanout = 4; REG Node = 'Q1\[9\]~reg0'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { Q1[9]~reg0 } "NODE_NAME" } } { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.223 ns) 1.261 ns c_a~reg0 2 REG LC_X51_Y10_N4 1 " "Info: 2: + IC(1.038 ns) + CELL(0.223 ns) = 1.261 ns; Loc. = LC_X51_Y10_N4; Fanout = 1; REG Node = 'c_a~reg0'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "1.261 ns" { Q1[9]~reg0 c_a~reg0 } "NODE_NAME" } } { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.223 ns ( 17.68 % ) " "Info: Total cell delay = 0.223 ns ( 17.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.038 ns ( 82.32 % ) " "Info: Total interconnect delay = 1.038 ns ( 82.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "1.261 ns" { Q1[9]~reg0 c_a~reg0 } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "1.261 ns" { Q1[9]~reg0 c_a~reg0 } { 0.000ns 1.038ns } { 0.000ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.034 ns - Smallest " "Info: - Smallest clock skew is 0.034 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.986 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.986 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 23 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 23; CLK Node = 'clk'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.616 ns) + CELL(0.542 ns) 2.986 ns c_a~reg0 2 REG LC_X51_Y10_N4 1 " "Info: 2: + IC(1.616 ns) + CELL(0.542 ns) = 2.986 ns; Loc. = LC_X51_Y10_N4; Fanout = 1; REG Node = 'c_a~reg0'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.158 ns" { clk c_a~reg0 } "NODE_NAME" } } { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.88 % ) " "Info: Total cell delay = 1.370 ns ( 45.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.616 ns ( 54.12 % ) " "Info: Total interconnect delay = 1.616 ns ( 54.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.986 ns" { clk c_a~reg0 } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "2.986 ns" { clk clk~out0 c_a~reg0 } { 0.000ns 0.000ns 1.616ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.952 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.952 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 23 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 23; CLK Node = 'clk'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.582 ns) + CELL(0.542 ns) 2.952 ns Q1\[9\]~reg0 2 REG LC_X52_Y7_N7 4 " "Info: 2: + IC(1.582 ns) + CELL(0.542 ns) = 2.952 ns; Loc. = LC_X52_Y7_N7; Fanout = 4; REG Node = 'Q1\[9\]~reg0'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.124 ns" { clk Q1[9]~reg0 } "NODE_NAME" } } { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.41 % ) " "Info: Total cell delay = 1.370 ns ( 46.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.582 ns ( 53.59 % ) " "Info: Total interconnect delay = 1.582 ns ( 53.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.952 ns" { clk Q1[9]~reg0 } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "2.952 ns" { clk clk~out0 Q1[9]~reg0 } { 0.000ns 0.000ns 1.582ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.986 ns" { clk c_a~reg0 } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "2.986 ns" { clk clk~out0 c_a~reg0 } { 0.000ns 0.000ns 1.616ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.952 ns" { clk Q1[9]~reg0 } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "2.952 ns" { clk clk~out0 Q1[9]~reg0 } { 0.000ns 0.000ns 1.582ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 26 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 26 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "1.261 ns" { Q1[9]~reg0 c_a~reg0 } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "1.261 ns" { Q1[9]~reg0 c_a~reg0 } { 0.000ns 1.038ns } { 0.000ns 0.223ns } } } { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.986 ns" { clk c_a~reg0 } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "2.986 ns" { clk clk~out0 c_a~reg0 } { 0.000ns 0.000ns 1.616ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.952 ns" { clk Q1[9]~reg0 } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "2.952 ns" { clk clk~out0 Q1[9]~reg0 } { 0.000ns 0.000ns 1.582ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { c_a~reg0 } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { c_a~reg0 } {  } {  } } } { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 26 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}