?? c_a.tan.qmsg
字號:
{ "Info" "ITDB_TSU_RESULT" "Q1\[1\]~reg0 clr clk 2.525 ns register " "Info: tsu for register \"Q1\[1\]~reg0\" (data pin = \"clr\", clock pin = \"clk\") is 2.525 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.467 ns + Longest pin register " "Info: + Longest pin to register delay is 5.467 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clr 1 PIN PIN_M2 23 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M2; Fanout = 23; PIN Node = 'clr'" { } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.872 ns) + CELL(0.870 ns) 5.467 ns Q1\[1\]~reg0 2 REG LC_X52_Y7_N1 4 " "Info: 2: + IC(3.872 ns) + CELL(0.870 ns) = 5.467 ns; Loc. = LC_X52_Y7_N1; Fanout = 4; REG Node = 'Q1\[1\]~reg0'" { } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "4.742 ns" { clr Q1[1]~reg0 } "NODE_NAME" } } { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.595 ns ( 29.18 % ) " "Info: Total cell delay = 1.595 ns ( 29.18 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.872 ns ( 70.82 % ) " "Info: Total interconnect delay = 3.872 ns ( 70.82 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "5.467 ns" { clr Q1[1]~reg0 } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "5.467 ns" { clr clr~out0 Q1[1]~reg0 } { 0.000ns 0.000ns 3.872ns } { 0.000ns 0.725ns 0.870ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 26 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.952 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.952 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 23 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 23; CLK Node = 'clk'" { } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.582 ns) + CELL(0.542 ns) 2.952 ns Q1\[1\]~reg0 2 REG LC_X52_Y7_N1 4 " "Info: 2: + IC(1.582 ns) + CELL(0.542 ns) = 2.952 ns; Loc. = LC_X52_Y7_N1; Fanout = 4; REG Node = 'Q1\[1\]~reg0'" { } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.124 ns" { clk Q1[1]~reg0 } "NODE_NAME" } } { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.41 % ) " "Info: Total cell delay = 1.370 ns ( 46.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.582 ns ( 53.59 % ) " "Info: Total interconnect delay = 1.582 ns ( 53.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.952 ns" { clk Q1[1]~reg0 } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "2.952 ns" { clk clk~out0 Q1[1]~reg0 } { 0.000ns 0.000ns 1.582ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "5.467 ns" { clr Q1[1]~reg0 } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "5.467 ns" { clr clr~out0 Q1[1]~reg0 } { 0.000ns 0.000ns 3.872ns } { 0.000ns 0.725ns 0.870ns } } } { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.952 ns" { clk Q1[1]~reg0 } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "2.952 ns" { clk clk~out0 Q1[1]~reg0 } { 0.000ns 0.000ns 1.582ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Q1\[0\] Q1\[1\]~reg0 7.703 ns register " "Info: tco from clock \"clk\" to destination pin \"Q1\[0\]\" through register \"Q1\[1\]~reg0\" is 7.703 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.952 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.952 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 23 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 23; CLK Node = 'clk'" { } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.582 ns) + CELL(0.542 ns) 2.952 ns Q1\[1\]~reg0 2 REG LC_X52_Y7_N1 4 " "Info: 2: + IC(1.582 ns) + CELL(0.542 ns) = 2.952 ns; Loc. = LC_X52_Y7_N1; Fanout = 4; REG Node = 'Q1\[1\]~reg0'" { } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.124 ns" { clk Q1[1]~reg0 } "NODE_NAME" } } { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.41 % ) " "Info: Total cell delay = 1.370 ns ( 46.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.582 ns ( 53.59 % ) " "Info: Total interconnect delay = 1.582 ns ( 53.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.952 ns" { clk Q1[1]~reg0 } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "2.952 ns" { clk clk~out0 Q1[1]~reg0 } { 0.000ns 0.000ns 1.582ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 26 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.595 ns + Longest register pin " "Info: + Longest register to pin delay is 4.595 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q1\[1\]~reg0 1 REG LC_X52_Y7_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y7_N1; Fanout = 4; REG Node = 'Q1\[1\]~reg0'" { } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { Q1[1]~reg0 } "NODE_NAME" } } { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.219 ns) + CELL(2.376 ns) 4.595 ns Q1\[0\] 2 PIN PIN_H1 0 " "Info: 2: + IC(2.219 ns) + CELL(2.376 ns) = 4.595 ns; Loc. = PIN_H1; Fanout = 0; PIN Node = 'Q1\[0\]'" { } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "4.595 ns" { Q1[1]~reg0 Q1[0] } "NODE_NAME" } } { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.376 ns ( 51.71 % ) " "Info: Total cell delay = 2.376 ns ( 51.71 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.219 ns ( 48.29 % ) " "Info: Total interconnect delay = 2.219 ns ( 48.29 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "4.595 ns" { Q1[1]~reg0 Q1[0] } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "4.595 ns" { Q1[1]~reg0 Q1[0] } { 0.000ns 2.219ns } { 0.000ns 2.376ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.952 ns" { clk Q1[1]~reg0 } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "2.952 ns" { clk clk~out0 Q1[1]~reg0 } { 0.000ns 0.000ns 1.582ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "4.595 ns" { Q1[1]~reg0 Q1[0] } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "4.595 ns" { Q1[1]~reg0 Q1[0] } { 0.000ns 2.219ns } { 0.000ns 2.376ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "Q2\[8\]~reg0 clr clk -1.674 ns register " "Info: th for register \"Q2\[8\]~reg0\" (data pin = \"clr\", clock pin = \"clk\") is -1.674 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.986 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.986 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 23 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 23; CLK Node = 'clk'" { } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.616 ns) + CELL(0.542 ns) 2.986 ns Q2\[8\]~reg0 2 REG LC_X52_Y10_N7 3 " "Info: 2: + IC(1.616 ns) + CELL(0.542 ns) = 2.986 ns; Loc. = LC_X52_Y10_N7; Fanout = 3; REG Node = 'Q2\[8\]~reg0'" { } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.158 ns" { clk Q2[8]~reg0 } "NODE_NAME" } } { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.88 % ) " "Info: Total cell delay = 1.370 ns ( 45.88 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.616 ns ( 54.12 % ) " "Info: Total interconnect delay = 1.616 ns ( 54.12 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.986 ns" { clk Q2[8]~reg0 } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "2.986 ns" { clk clk~out0 Q2[8]~reg0 } { 0.000ns 0.000ns 1.616ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 26 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.760 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.760 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clr 1 PIN PIN_M2 23 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M2; Fanout = 23; PIN Node = 'clr'" { } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.812 ns) + CELL(0.223 ns) 4.760 ns Q2\[8\]~reg0 2 REG LC_X52_Y10_N7 3 " "Info: 2: + IC(3.812 ns) + CELL(0.223 ns) = 4.760 ns; Loc. = LC_X52_Y10_N7; Fanout = 3; REG Node = 'Q2\[8\]~reg0'" { } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "4.035 ns" { clr Q2[8]~reg0 } "NODE_NAME" } } { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.948 ns ( 19.92 % ) " "Info: Total cell delay = 0.948 ns ( 19.92 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.812 ns ( 80.08 % ) " "Info: Total interconnect delay = 3.812 ns ( 80.08 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "4.760 ns" { clr Q2[8]~reg0 } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "4.760 ns" { clr clr~out0 Q2[8]~reg0 } { 0.000ns 0.000ns 3.812ns } { 0.000ns 0.725ns 0.223ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.986 ns" { clk Q2[8]~reg0 } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "2.986 ns" { clk clk~out0 Q2[8]~reg0 } { 0.000ns 0.000ns 1.616ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "4.760 ns" { clr Q2[8]~reg0 } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "4.760 ns" { clr clr~out0 Q2[8]~reg0 } { 0.000ns 0.000ns 3.812ns } { 0.000ns 0.725ns 0.223ns } } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 27 15:44:33 2009 " "Info: Processing ended: Fri Feb 27 15:44:33 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -