?? ac97.c
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/********************************************************************************
*
* Project Name : S3C6400 Validation
*
* Copyright 2006 by Samsung Electronics, Inc.
* All rights reserved.
*
* Project Description :
* This software is only for verifying functions of the S3C6400.
* Anybody can use this software without our permission.
*
*--------------------------------------------------------------------------------
*
* File Name : AC97.c
*
* File Description :
*
* Author : Yoh-Han Lee
* Dept. : AP Development Team
* Created Date : 2007/03/09
* Version : 0.2
*
* History
* - Version 0.1 (Y.H.Lee, 2007/03/09)
* -> Only available with STAC9767 AC97 Codec.
* - Version 0.2 (Y.H.Lee, 2007/04/04)
* -> Working with WM9713 AC97 Codec.
*
********************************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <ctype.h>
#include "def.h"
#include "option.h"
#include "library.h"
#include "sfr6400.h"
#include "system.h"
#include "intc.h"
#include "gpio.h"
#include "dma.h"
#include "sysc.h"
#include "ac97.h"
static DMAC oAc97Dma;
static u32 uOutputVolume;
static u8 uCodecReadyIrq;
static u16 uAc97RecDone;
static u16 uAc97PlayDone;
static volatile u32 * uRecBuffer;
static volatile u32 * uEndRecBuffer;
void AC97_SetPort(AC97_PORT ePort)
{
if (ePort == PORT0)
{
//Set GPD: AC97 Port
GPIO_SetFunctionAll(eGPIO_D, 0x44444, 0);
GPIO_SetPullUpDownAll(eGPIO_D, 0x0);
}
else if (ePort == PORT1)
{
//Set GPE: AC97 Port
GPIO_SetFunctionAll(eGPIO_E, 0x44444, 0);
GPIO_SetPullUpDownAll(eGPIO_E, 0x0);
}
Delay(1000);
}
bool AC97_Init(void)
{
u32 i=0;
Disp("\nAC97 Initialization...\n");
//Codec Ready Check using Codec Ready Interrupt
//Cold Reset
AC97_ColdReset();
uCodecReadyIrq =0;
INTC_SetVectAddr(NUM_AC97, Isr_AC97_CodecReady);
INTC_Enable(NUM_AC97);
AC97_EnableInt(CODEC_READY_INT);
while(!uCodecReadyIrq)
{
Disp(".");
Delay(3000);
i++;
if(i==20)
break;
}
Disp("\n");
if(i>=20)
{
Disp("\nAC97 codec is not ready.");
Disp("\nCheck on connection between AP and AC97 CODEC.\n");
Disp("\nBye. ");
return false;
}
else
{
return true;
}
}
void AC97_SetTransferCh(AC97_CHANNEL eCh, AC97_TRANSFER_MODE eTransferMode)
{
u32 uEnTransferCh;
uEnTransferCh= Inp32(AC97_BASE+rACGLBCTRL);
if(eCh == PCM_OUT)
{
uEnTransferCh =
(eTransferMode == PIO) ? (uEnTransferCh |(1<<12)) :
(eTransferMode == DMA) ? (uEnTransferCh |(2<<12)) : (uEnTransferCh & ~(3<<12));
}
else if(eCh == PCM_IN)
{
uEnTransferCh =
(eTransferMode == PIO) ? (uEnTransferCh|(1<<10)) :
(eTransferMode == DMA) ? (uEnTransferCh|(2<<10)) : (uEnTransferCh & ~(3<<10));
}
else if(eCh == MIC_IN)
{
uEnTransferCh =
(eTransferMode == PIO) ? (uEnTransferCh|(1<<8)) :
(eTransferMode == DMA) ? (uEnTransferCh|(2<<8)) : (uEnTransferCh & ~(3<<8));
}
uEnTransferCh |= (3<<2);
AC97Outp32(rACGLBCTRL, uEnTransferCh);
Delay(1000);
//AC97_ControllerState();
}
void AC97_WarmReset(void)
{
u32 uGlobalCon;
Disp("\n=>Warm Reset\n");
AC97_CodecCmd(READ,0x26,0x0); //To avoid issuing unwanted command to Codec after warm reset
uGlobalCon = Inp32(AC97_BASE+rACGLBCTRL);
uGlobalCon |= (1<<1);
AC97Outp32(rACGLBCTRL, uGlobalCon);
Delay(1000);
uGlobalCon &= ~(1<<1);
AC97Outp32(rACGLBCTRL, uGlobalCon);
AC97_ControllerState();
Delay(1000);
uGlobalCon |= (1<<2);
AC97Outp32(rACGLBCTRL, uGlobalCon);
AC97_ControllerState();
uGlobalCon |= (1<<3);
AC97Outp32(rACGLBCTRL, uGlobalCon);
Delay(1000);
//AC97_CodecCmd(WRITE,0x00,0x683F);
AC97_ControllerState();
Disp("AC97 Codec Powerdown Ctrl/Stat Reg. Value (at 0x26): 0x%x\n", AC97_CodecCmd(READ,0x26,0x0000));
}
void AC97_ColdReset(void)
{
u32 uGlobalCon;
Disp("\n=>Cold Reset\n");
//uGlobalCon = Inp32(AC97_BASE+rACGLBCTRL);
uGlobalCon = (1<<0);
AC97Outp32(rACGLBCTRL, uGlobalCon);
Delay(1000);
uGlobalCon &= ~(1<<0);
AC97Outp32(rACGLBCTRL, uGlobalCon);
Delay(1000);
uGlobalCon = (1<<0);
AC97Outp32(rACGLBCTRL, uGlobalCon);
Delay(1000);
uGlobalCon &= ~(1<<0);
AC97Outp32(rACGLBCTRL, uGlobalCon);
Delay(1000);
AC97_ControllerState();
#if (AC97_CODEC_NAME== WM9713)
AC97_WarmReset();
#endif
uGlobalCon |= (1<<2);
AC97Outp32(rACGLBCTRL, uGlobalCon);
AC97_ControllerState();
uGlobalCon |= (1<<3);
AC97Outp32(rACGLBCTRL, uGlobalCon);
AC97_ControllerState();
//Disp("AC97 Codec Powerdown Ctrl/Stat Reg. Value (at 0x26): 0x%x\n", AC97_CodecCmd(READ,0x26,0x0000));
}
void AC97_CodecInitPD(void)
{
#if (AC97_CODEC_NAME== STAC9767)
Disp("\nSoft Reset\n");
AC97_CodecCmd(WRITE,0x00,0x683F); //Codec Soft Reset : 16bit In/Out
Disp("AC97 Codec 0x26 Reg.: 0x%x\n\n", AC97_CodecCmd(READ,0x26,0x0000));
#endif
}
u16 AC97_CodecCmd(AC97_CMD eCmd, u8 uCmdOffset, u16 uCmdData)
{
u32 uState;
u16 uCodecStat;
if(eCmd == WRITE)
{
AC97Outp32(rACCODECCMD, (0<<23)|(uCmdOffset<<16)|(uCmdData<<0));
Delay(10);
return 0;
}
else if (eCmd == READ)
{
AC97Outp32(rACCODECCMD, (1<<23)|(uCmdOffset<<16)|(uCmdData<<0));
Delay(1000);
uState= Inp32(AC97_BASE+rACCODECSTAT);
uCodecStat = (u16)(uState & 0xFFFF);
Delay(1000);
return uCodecStat;
}
else
return 0;
}
void AC97_ControllerState(void)
{
u32 uState;
uState= Inp32(AC97_BASE+rACGLBSTAT);
if((uState & 0x7) == 0)
Disp("AC97 Controller State: Idle\n");
else if ((uState & 0x7) == 1)
Disp("AC97 Controller State: Init\n");
else if ((uState & 0x7) == 2)
Disp("AC97 Controller State: Ready\n");
else if ((uState & 0x7) == 3)
Disp("AC97 Controller State: Active\n");
else if ((uState & 0x7) == 4)
Disp("AC97 Controller State: LP\n");
else if ((uState & 0x7) == 5)
Disp("AC97 Controller State: Warm\n");
}
void AC97_EnableInt(AC97_INT eInt)
{
u32 uInt;
uInt= Inp32(AC97_BASE+rACGLBCTRL);
if(eInt == CODEC_READY_INT)
uInt |= 1<<22;
else if (eInt == PCMOUT_UNDERRUN_INT)
uInt |= 1<<21;
else if (eInt == PCMIN_OVERRUN_INT)
uInt |= 1<<20;
else if (eInt == MICIN_OVERRUN_INT)
uInt |= 1<<19;
else if (eInt == PCMOUT_THRESHOLD_INT)
uInt |= 1<<18;
else if (eInt == PCMIN_THRESHOLD_INT)
uInt |= 1<<17;
else if (eInt == MICIN_THRESHOLD_INT)
uInt |= 1<<16;
//Disp("rACGLBCTRL: 0x%x\n", uInt);
AC97Outp32(rACGLBCTRL, uInt);
}
void AC97_DisableInt(AC97_INT eInt)
{
u32 uInt;
uInt= Inp32(AC97_BASE+rACGLBCTRL);
if(eInt == CODEC_READY_INT)
AC97Outp32(rACGLBCTRL, uInt & ~(1<<22));
else if (eInt == PCMOUT_UNDERRUN_INT)
AC97Outp32(rACGLBCTRL, uInt & ~(1<<21));
else if (eInt == PCMIN_OVERRUN_INT)
AC97Outp32(rACGLBCTRL, uInt & ~(1<<20));
else if (eInt == MICIN_OVERRUN_INT)
AC97Outp32(rACGLBCTRL, uInt & ~(1<<19));
else if (eInt == PCMOUT_THRESHOLD_INT)
AC97Outp32(rACGLBCTRL, uInt & ~(1<<18));
else if (eInt == PCMIN_THRESHOLD_INT)
AC97Outp32(rACGLBCTRL, uInt & ~(1<<17));
else if (eInt == MICIN_THRESHOLD_INT)
AC97Outp32(rACGLBCTRL, uInt & ~(1<<16));
}
void AC97_ClearInt(AC97_INT eInt)
{
u32 uInt;
uInt= Inp32(AC97_BASE+rACGLBCTRL);
if(eInt == CODEC_READY_INT)
AC97Outp32(rACGLBCTRL, uInt | 1<<30);
else if (eInt == PCMOUT_UNDERRUN_INT)
AC97Outp32(rACGLBCTRL, uInt | 1<<29);
else if (eInt == PCMIN_OVERRUN_INT)
AC97Outp32(rACGLBCTRL, uInt | 1<<28);
else if (eInt == MICIN_OVERRUN_INT)
AC97Outp32(rACGLBCTRL, uInt | 1<<27);
else if (eInt == PCMOUT_THRESHOLD_INT)
AC97Outp32(rACGLBCTRL, uInt | 1<<26);
else if (eInt == PCMIN_THRESHOLD_INT)
AC97Outp32(rACGLBCTRL, uInt | 1<<25);
else if (eInt == MICIN_THRESHOLD_INT)
AC97Outp32(rACGLBCTRL, uInt | 1<<24);
}
u16 AC97_SelectSamplingRate(void)
{
u32 i;
Disp("\nSelect ADC/DAC Rate\n");
Disp("0:8KHz, 1:22.05kHz, 2:44.1kHz, 3:48kHz\n");
i = GetIntNum();
if(i==0)
return 8000;
else if(i==1)
return 22100;
else if(i==1)
return 44100;
else
return 48000;
}
void AC97_InitCodecPCMIn( u16 uAc97Fs)
{
#if (AC97_CODEC_NAME== STAC9767)
AC97_CodecCmd(WRITE,0x00,0x683F); //codec soft reset
AC97_CodecCmd(WRITE,0x2A,0x0001); //variable rate enable
Disp("VRA Enable(1)/Disable(0): 0x%x\n",(0x1&AC97_CodecCmd(READ,0x2A,0x0001)));
if(uAc97Fs==8000){
//ADC Sampling frequency 8kHz
AC97_CodecCmd(WRITE,0x32,0x1f40);
}
else if(uAc97Fs==48000){
//ADC Sampling frequency 48kHz
AC97_CodecCmd(WRITE,0x32,0xbb80);
}
else if(uAc97Fs==44100){
//ADC Sampling frequency 44.1kHz
AC97_CodecCmd(WRITE,0x32,0xac44);
}
else if(uAc97Fs==22050){
//ADC Sampling frequency 22.05kHz
AC97_CodecCmd(WRITE,0x32,0x5622);
}
AC97_CodecCmd(WRITE,0x26,(1<<9)); //all power on except DAC Block
Disp("\nAC97 Codec 0x26 Reg.: 0x%x\n\n", AC97_CodecCmd(READ,0x26,0x0000));
AC97_CodecCmd(WRITE,0x10,0x1010); //line in volume on
AC97_CodecCmd(WRITE,0x6e,0x0000); //All Analog Mode, ADC Input select => left slot3, right slot4
AC97_CodecCmd(WRITE,0x1a,0x0505); //record source select => Stereo Mix
AC97_CodecCmd(WRITE,0x1c,0x0909); //record gain is initial
AC97_CodecCmd(WRITE,0x78,0x0001); //ADC HPF Bypass
AC97_CodecCmd(WRITE,0x20,0x0000); //General Reg.
//AC97_CodecCmd(READ,0x10,0x0000); //Line In volume
#elif (AC97_CODEC_NAME== WM9713)
AC97_CodecCmd(WRITE,0x26, 0x4f00); // Enable PR5(Internal Clock, AC-link I/F)
AC97_CodecCmd(WRITE,0x26, 0x4700); // Enable PR3(VREF, I/P PGA's, DAC's, ADC's, Mixer, O/P's)
//Disp("AC97 Codec 0x26 Reg.: 0x%x\n\n", AC97_CodecCmd(READ,0x26,0x0000));
AC97_CodecCmd(WRITE,0x3c, 0xfbff); // Enable MBIAS generator
Delay(1000);
AC97_CodecCmd(WRITE,0x26, 0x4300); // Enable PR2(I/P PGA's and mixers)
AC97_CodecCmd(WRITE,0x3C, 0xfbcf); // Enable ADC L/R
AC97_CodecCmd(WRITE,0x26, 0x4200); // Enable Stereo ADC
AC97_CodecCmd(WRITE,0x26, 0x0200); // Enable PR6 (O/P PGA's)
AC97_CodecCmd(WRITE,0x3E, 0xff9f); // Enable LINE L/R PGA
AC97_CodecCmd(WRITE,0x2A,0x1); //Variable Rate Enable
Disp("VRA Enable(1)/Disable(0): 0x%x\n",(0x1&AC97_CodecCmd(READ,0x2A,0x0001)));
if(uAc97Fs==8000){
//ADC Sampling frequency 8kHz
AC97_CodecCmd(WRITE,0x32,0x1f40);
}
else if(uAc97Fs==48000){
//ADC Sampling frequency 48kHz
AC97_CodecCmd(WRITE,0x32,0xbb80);
}
else if(uAc97Fs==44100){
//ADC Sampling frequency 44.1kHz
AC97_CodecCmd(WRITE,0x32,0xac44);
}
else if(uAc97Fs==22050){
//ADC Sampling frequency 22.05kHz
AC97_CodecCmd(WRITE,0x32,0x5622);
}
Disp("\nAC97 Codec 0x32 Reg.: 0x%x\n\n", AC97_CodecCmd(READ,0x32,0x0000));
AC97_CodecCmd(WRITE,0x14, 0xfe12); // Record Mux Source Selection: LINE L/R
AC97_CodecCmd(WRITE,0x12, 0x1010); // Unmute ADC and Set ADC Recoding Volume
#endif
}
void AC97_InitCodecPCMOut(u16 uAc97Fs)
{
#if (AC97_CODEC_NAME== STAC9767)
AC97_CodecCmd(WRITE,0x00,0x683F); //codec soft reset
AC97_CodecCmd(WRITE,0x2A,0x0001); //variable rate enable
//Disp("\nVRA Enable(1)/Disable(0): 0x%x\n", (0x1&AC97_CodecCmd(READ,0x2A,0x0001)));
if(uAc97Fs==8000){
//DAC Sampling frequency 8kHz
AC97_CodecCmd(WRITE,0x2C,0x1f40);
}
else if(uAc97Fs==48000){
//DAC Sampling frequency 48kHz
AC97_CodecCmd(WRITE,0x2C,0xbb80);
}
else if(uAc97Fs==44100){
//DAC Sampling frequency 44.1kHz
AC97_CodecCmd(WRITE,0x2C,0xac44);
}
else if(uAc97Fs==22050){
//DAC Sampling frequency 22.05kHz
AC97_CodecCmd(WRITE,0x2C,0x5622);
}
AC97_CodecCmd(WRITE,0x26, (1<<8)); // all power on except ADC blcok
Disp("AC97 Codec 0x26 Reg.: 0x%x\n\n", AC97_CodecCmd(READ,0x26,0x0000));
AC97_CodecCmd(WRITE,0x18,0x0000); // PCM out volume on
AC97_CodecCmd(WRITE,0x20,0x0000); // general purpose
AC97_CodecCmd(WRITE,0x04,0x1A1A); // Aux out(HP out) volume on
uOutputVolume = AC97_CodecCmd(READ,0x04,0x00000); //HP out volume
#elif (AC97_CODEC_NAME== WM9713)
AC97_CodecCmd(WRITE,0x26, 0x4f00); // Enable PR5(Internal Clock, AC-link I/F)
AC97_CodecCmd(WRITE,0x26, 0x4700); // Enable PR3(VREF, I/P PGA's, DAC's, ADC's, Mixer, O/P's)
//Disp("AC97 Codec 0x26 Reg.: 0x%x\n\n", AC97_CodecCmd(READ,0x26,0x0000));
AC97_CodecCmd(WRITE,0x3c, 0xfbff); // Enable MBIAS generator
Delay(1000);
AC97_CodecCmd(WRITE,0x26, 0x4300); // Enable PR2(I/P PGA's and mixers)
AC97_CodecCmd(WRITE,0x3C, 0xfbf3); // Enable HPL/R Mixer
AC97_CodecCmd(WRITE,0x26, 0x4100); // Enable PR1(Stereo DAC)
AC97_CodecCmd(WRITE,0x3C, 0xfb33); // Enable DAC L/R
AC97_CodecCmd(WRITE,0x26, 0x0100); // Enable PR6 (O/P PGA's)
AC97_CodecCmd(WRITE,0x3E, 0xf9ff); // Enable PR6 (O/P PGA's)
AC97_CodecCmd(WRITE,0x2A,0x1); //Variable Rate Enable
Disp("VRA Enable(1)/Disable(0): 0x%x\n",(0x1&AC97_CodecCmd(READ,0x2A,0x0001)));
if(uAc97Fs==8000){
//DAC Sampling frequency 8kHz
AC97_CodecCmd(WRITE,0x2C,0x1f40);
}
else if(uAc97Fs==48000){
//DAC Sampling frequency 48kHz
AC97_CodecCmd(WRITE,0x2C,0xbb80);
}
else if(uAc97Fs==44100){
//DAC Sampling frequency 44.1kHz
AC97_CodecCmd(WRITE,0x2C,0xac44);
}
else if(uAc97Fs==22050){
//DAC Sampling frequency 22.05kHz
AC97_CodecCmd(WRITE,0x2C,0x5622);
}
Disp("\nAC97 Codec 0x2C Reg.: 0x%x\n\n", AC97_CodecCmd(READ,0x2C,0x0000));
AC97_CodecCmd(WRITE,0x1c, 0x00a0); // HPL/R PGA input select HPMIXL/R
AC97_CodecCmd(WRITE,0x04,0x0707); // Set HPL/R Volume
uOutputVolume = AC97_CodecCmd(READ,0x04,0x00000); //HP out volume
AC97_CodecCmd(WRITE,0x0c,0x6808); // Unmute DAC to HP mixer path
AC97_CodecCmd(WRITE,0x04,0x0A0A); // Unmute HPL/R
#endif
}
void AC97_InitCodecMICIn(u16 uAc97Fs)
{
#if (AC97_CODEC_NAME== STAC9767)
AC97_CodecCmd(WRITE,0x00,0x683F); //codec soft reset
AC97_CodecCmd(WRITE,0x2A,0x0001); //variable rate enable
Disp("VRA Enable(1)/Disable(0): 0x%x\n",(0x1&AC97_CodecCmd(READ,0x2A,0x0001)));
if(uAc97Fs==8000){
//ADC Sampling frequency 8kHz
AC97_CodecCmd(WRITE,0x32,0x1f40);
}
if(uAc97Fs==48000){
//ADC Sampling frequency 48kHz
AC97_CodecCmd(WRITE,0x32,0xbb80);
}
else if(uAc97Fs==44100){
//ADC Sampling frequency 44.1kHz
AC97_CodecCmd(WRITE,0x32,0xac44);
}
else if(uAc97Fs==22050){
//ADC Sampling frequency 22.05kHz
AC97_CodecCmd(WRITE,0x32,0x5622);
}
AC97_CodecCmd(WRITE,0x26,(1<<9)); //all power on except DAC Block
Disp("\nAC97 Codec 0x26 Reg.: 0x%x\n\n", AC97_CodecCmd(READ,0x26,0x0000));
AC97_CodecCmd(WRITE,0x20,0x0000); //MIC1 Selected
AC97_CodecCmd(WRITE,0x6e,0x0024); //ADC Input Slot => left slot6, right slot9, MIC GAIN VAL =1
AC97_CodecCmd(WRITE,0x0e,0x0040); //BOOSTEN =1
AC97_CodecCmd(WRITE,0x1a,0x0000); //Left, Right => MIC
AC97_CodecCmd(WRITE,0x1c,0xff);
AC97_CodecCmd(WRITE,0x78,0x0001); //ADC HPF Bypass
//AC97_CodecCmd(READ,0x1c,0x0000); //Record Volume
#elif (AC97_CODEC_NAME== WM9713)
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