/********************************************************************************
* 
*	Project Name : S3C6400 Validation
*
*	Copyright 2006 by Samsung Electronics, Inc.
*	All rights reserved.
*
*	Project Description :
*		This software is only for verifying functions of the S3C6400.
*		Anybody can use this software without our permission.
*  
*--------------------------------------------------------------------------------
* 
*	File Name : PCM_test.c
*	File Description :
*
*	Author	: Yoh-Han Lee
*	Dept. : AP Development Team
*
*	Version : 0.2
* 
*	History
*	- Version 0.1 (2007/03/16)
*	  -> Available with AK2440 PCM Codec.
*   - Version 0.2 (2007/04/19)
*     -> Also, working with WM8753 PCM Codec.
*
********************************************************************************/

#ifndef __PCM_H__
#define __PCM_H__
 
  
#ifdef __cplusplus
extern "C" {
#endif

#include "def.h"
#include "option.h"
#include "library.h"
#include "sfr6400.h"
#include "system.h"
#include "sysc.h"
#include "dma.h"

// PCM CODEC NAME 
#define PCM_CODEC_NAME				WM8753	
#define AK2430						1		//This Codec is not in the 
#define WM9713						2		//There is some noise in WM9713 ADC Path 
#define WM8753						3		

// PCM MODULE SELECTION 
#define PCM_MODULE					PCM_MODULE1
#define PCM_MODULE0					1
#define PCM_MODULE1					2

// PCM SERIAL CLOCK SELECTION
#define PCMSCLK 	    			256000

#define PCMSCLK_128K				128000
#define PCMSCLK_256K				256000
#define PCMSCLK_512K				512000

// PCM CLOCK SOURCE SELECTION
#define PCMCLKSOURCE 	    		PCMCLKSOURCE_MOUT_EPLL
#define PCMCLKSOURCE_MOUT_EPLL		1
#define PCMCLKSOURCE_DOUT_MPLL		2
#define PCMCLKSOURCE_FIN_EPLL		3
#define PCMCLKSOURCE_PCMCDCLK		4
#define PCMCLKSOURCE_PCLK			5

// PCM TIMING POS_MSB_WR/RD
#define PCM_MSB_POS					AFTER_PCMSYNC_HIGH
#define DURING_PCMSYNC_HIGH			1
#define AFTER_PCMSYNC_HIGH			2

///////////////////////////////////////////////////////////////
#define PCM_FS						8000	//Sampling Frequency = 8KHz
#define PCM_REC_LEN 				0xfffff*4/8
#define PCM_REC_BUF  				CODEC_MEM_ST	//0x51000000


enum PCM_SFR
{

	rPCMCTRL = 0x0,		
	rPCMCLKCTL = 0x4,		
	rPCMTXFIFO = 0x8,		
	rPCMRXFIFO = 0xc,   	
	rPCMIRQCTL = 0x10,		
	rPCMIRQSTAT= 0x14,		
	rPCMFIFOSTAT = 0x18,	
	rPCMCLRINT = 0x20		
};


#if(PCM_MODULE == PCM_MODULE0)
	#define PCMOutp32(offset, x) Outp32(PCM0_BASE+offset, x)
	#define PCMInp32(offset) Inp32(PCM0_BASE+offset)
	#define PCMInp16(offset) Inp16(PCM0_BASE+offset)
	
#elif(PCM_MODULE == PCM_MODULE1)
	#define PCMOutp32(offset, x) Outp32(PCM1_BASE+offset, x)
	#define PCMInp32(offset) Inp32(PCM1_BASE+offset)
	#define PCMInp16(offset) Inp16(PCM1_BASE+offset)
	
#endif

#define IICOutp32(offset, x) Outp32(offset, x)
#define IICInp32(offset) Inp32(offset)

#define PCM_SCLK_EN				(1<<19)
#define PCM_PCM_ENABLE			(1<<0)
#define PCM_RXFIFO_EN   		(1<<1)
#define PCM_TXFIFO_EN			(1<<2)
#define RX_MSB_POS0				(0<<3)
#define RX_MSB_POS1				(1<<3)
#define TX_MSB_POS0				(0<<4)
#define TX_MSB_POS1				(1<<4)
#define PCM_RX_DMA_EN			(1<<5)
#define PCM_TX_DMA_EN			(1<<6)
#define RXFIFO_DIPSTICK(n)		(((n)&0x3f) <<7)
#define TXFIFO_DIPSTICK(n)		(((n)&0x3f) <<13)

#if 0	//For PCM SFR W/R Test
REGINFO		sPCMRegInfo[] = 
{ 

	{"			", PCM0_BASE+0x00, 32, RW, DPDB, 0, 0},   
	{"			", PCM0_BASE+0x04, 32, RW, DPDB, 0, 0},
	{"			", PCM0_BASE+0x08, 32, RW, DPDB, 0, 0},
	{"			", PCM0_BASE+0x0C, 32, RW, DPDB, 0, 0},
	{"			", PCM0_BASE+0x10, 32, RW, DPDB, 0, 0},   
	{"			", PCM0_BASE+0x14, 32, RW, DPDB, 0, 0},
	{"			", PCM0_BASE+0x18, 32, RW, DPDB, 0, 0},
	{"			", PCM0_BASE+0x20, 32, RW, DPDB, 0, 0},   

	{"			", PCM1_BASE+0x00, 32, RW, DPDB, 0, 0},   
	{"			", PCM1_BASE+0x04, 32, RW, DPDB, 0, 0},
	{"			", PCM1_BASE+0x08, 32, RW, DPDB, 0, 0},
	{"			", PCM1_BASE+0x0C, 32, RW, DPDB, 0, 0},
	{"			", PCM1_BASE+0x10, 32, RW, DPDB, 0, 0},   
	{"			", PCM1_BASE+0x14, 32, RW, DPDB, 0, 0},
	{"			", PCM1_BASE+0x18, 32, RW, DPDB, 0, 0},
	{"			", PCM1_BASE+0x20, 32, RW, DPDB, 0, 0},   

};
#endif

////////////////////////////////////////////////////////
typedef struct
{
	u32 m_uNumDma;
	DMASELECT_eID m_eDmaId;
	DMA_UNIT m_eDmaUnit;
	DMA_CH m_eDmaCh;
	u32 m_uPcmRxFifoAddr;
	u32 m_uPcmTxFifoAddr;
	DREQ_SRC m_eDreqSrc;
	u32 m_uNumInt;
	
}PCM;

typedef enum 
{
	PCM_PORT0, PCM_PORT1
}PCM_PORT;

typedef enum
{
	PCM_MOUT_EPLL, PCM_DOUT_MPLL, PCM_FIN_EPLL, PCM_PCMCDCLK, PCM_PCLK
}PCM_CLKSRC;

typedef enum 
{
	TRANSFER_DONE, TXFIFO_EMPTY, TXFIFO_ALMOST_EMPTY, TXFIFO_FULL, 
	TXFIFO_ALMOST_FULL, TXFIFO_ERROR_STARVE,      TXFIFO_ERROR_OVERFLOW,
	RXFIFO_EMPTY, RXFIFO_ALMOST_EMPTY, RX_FIFO_FULL, RX_FIFO_ALMOST_FULL,
	RXFIFO_ERROR_STARVE, RXFIFO_ERROR_OVERFLOW
}PCM_INT;

typedef enum
{
	SCLK_128K, SCLK_256K, SCLK_512K
} PCM_SCLK;

///////////////////////////////////////////////////////////////////////////////////////
void PCM_SetPort(PCM_PORT ePort);
void PCM_CodecInitPCMOut(PCM_SCLK ePcmSclk);

void PCM_CodecInitPCMIn(PCM_SCLK ePcmSclk);
void PCM_CodecExitPCMOut(void);
void PCM_CodecInitPCMIn(PCM_SCLK ePcmSclk);
void PCM_CodecExitPCMIn(void);

void PCM_PCMInDMA(u32 uRecBufferAddr, u32 uPcmSize, PCM_CLKSRC ePcmClkSrc);
void PCM_PCMOutDMA(u32 uRecBufferAddr, u32 uPcmSize, PCM_CLKSRC ePcmClkSrc);

void PCM_PCMInInt(u32 uRecBufferAddr, u32 uPcmSize, PCM_CLKSRC ePcmClkSrc);
void PCM_PCMOutInt(u32 uRecBufferAddr, u32 uPcmSize, PCM_CLKSRC ePcmClkSrc);

void PCM_ClearInt(void);
void PCM_EnableInt(PCM_INT ePcmInt);
void PCM_DisableInt(void);

void PCM_SelClkSrc(PCM_PORT ePort, PCM_CLKSRC eClkSrc);
void PCM_GetClkValAndClkDir(u32* uSclkDiv, u32* uSyncDiv, PCM_CLKSRC ePcmClkSrc);

void PCM_CODEC_IICWrite(u32 slvAddr, u32 addr, u8 data);
u8 PCM_CODEC_IICRead(u32 slvAddr, u8 addr);

void __irq Isr_PCM_PCMIn_DMADone(void);
void __irq Isr_PCM_PCMOut_DMADone(void);
void __irq Isr_PCM_PCMIn(void);
void __irq Isr_PCM_PCMOut(void);

#ifdef __cplusplus
}
#endif

#endif /*__PCM_H__*/