?? lcd.h
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/********************************************************************************
*
* Project Name : S3C6400 Validation
*
* Copyright 2006 by Samsung Electronics, Inc.
* All rights reserved.
*
* Project Description :
* This software is only for verifying functions of the S3C6400.
* Anybody can use this software without our permission.
*
*--------------------------------------------------------------------------------
*
* File Name : lcd.h
*
* File Description :
*
* Author : Yoh-Han Lee
* Dept. : AP Development Team
* Created Date : 2006/12/27
* Version : 0.2
*
* History
* - Created (2006/12/27)
* - Release Ver 0.1 (2007/03/29)
* - Release Ver 0.2 (2007/06/07)
********************************************************************************/
#ifndef __LCD_H__
#define __LCD_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "def.h"
#include "sfr6400.h"
#include "library.h"
#include "gpio.h"
#include "Option.h"
/////////////////////////////////////////////////////
// LCD Module Type
#define LCD_MODULE_TYPE LTE480WV_RGB
#define LTE480WV_RGB 0
#define LTV350QV_RGB 1
#define LTS222QV_CPU 2
#define LTS222QV_SRGB 3
#define LTP700WV_RGB 4
#define LTV300GV_RGB 5
/////////////////////////////////////////////////////
// I80 CPU I/F CS
#define LCD_CPUIF_CS CS_SUB
#define CS_MAIN 0
#define CS_SUB 1
/////////////////////////////////////////////////////
// LCD Clock Source Selection
#define LCD_CLOCK_SOURCE LCLK_MOUT_EPLL
#define LCLK_HCLK 1
#define LCLK_MOUT_EPLL 2
#define LCLK_DOUT_MPLL 3
#define LCLK_FIN_EPLL 4
#define LCLK_27M 5
/////////////////////////////////////////////////////
// LCD Frame Rate
#define LCD_FRM_RATE 60 //LCD Frame Rate (Hz)
/////////////////////////////////////////////////////
// LCD Frame Buffer Start Address
#define LCD_FRAMEBUFFER_ST CODEC_MEM_ST
/////////////////////////////////////////////////////
// LCD Special Function Registers
enum LCD_SFR
{
//Video Control
rVIDCON0 = 0x000,
rVIDCON1 = 0x004,
rVIDCON2 = 0x008,
//Video Time Control
rVIDTCON0 = 0x010,
rVIDTCON1 = 0x014,
rVIDTCON2 = 0x018,
rVIDTCON3 = 0x01c,
//Window Control
rWINCON0 = 0x020,
rWINCON1 = 0x024,
rWINCON2 = 0x028,
rWINCON3 = 0x02C,
rWINCON4 = 0x030,
//Video Window Position Control
rVIDOSD0A = 0x040,
rVIDOSD0B = 0x044,
rVIDOSD0C = 0x048,
rVIDOSD1A = 0x050,
rVIDOSD1B = 0x054,
rVIDOSD1C = 0x058,
rVIDOSD1D = 0x05C,
rVIDOSD2A = 0x060,
rVIDOSD2B = 0x064,
rVIDOSD2C = 0x068,
rVIDOSD2D = 0x06c,
rVIDOSD3A = 0x070,
rVIDOSD3B = 0x074,
rVIDOSD3C = 0x078,
rVIDOSD4A = 0x080,
rVIDOSD4B = 0x084,
rVIDOSD4C = 0x088,
//Window Buffer Start Address
rVIDW00ADD0B0 = 0x0A0,
rVIDW00ADD0B1 = 0x0A4,
rVIDW01ADD0B0 = 0x0A8,
rVIDW01ADD0B1 = 0x0AC,
rVIDW02ADD0 = 0x0B0,
rVIDW03ADD0 = 0x0B8,
rVIDW04ADD0 = 0x0C0,
//Window Buffer End Address
rVIDW00ADD1B0 = 0x0D0,
rVIDW00ADD1B1 = 0x0D4,
rVIDW01ADD1B0 = 0x0D8,
rVIDW01ADD1B1 = 0x0DC,
rVIDW02ADD1 = 0x0E0,
rVIDW03ADD1 = 0x0E8,
rVIDW04ADD1 = 0x0F0,
//Window Buffer Size
rVIDW00ADD2 = 0x100,
rVIDW01ADD2 = 0x104,
rVIDW02ADD2 = 0x108,
rVIDW03ADD2 = 0x10C,
rVIDW04ADD2 = 0x110,
//Indicate the Video Interrupt Control
rVIDINTCON0 = 0x130,
//Video Interrupt Pending
rVIDINTCON1 = 0x134,
//Color Key Control/Value
rW1KEYCON0 = 0x140,
rW1KEYCON1 = 0x144,
rW2KEYCON0 = 0x148,
rW2KEYCON1 = 0x14C,
rW3KEYCON0 = 0x150,
rW3KEYCON1 = 0x154,
rW4KEYCON0 = 0x158,
rW4KEYCON1 = 0x15C,
//DithMode
rDITHMODE = 0x170,
//Window Control
rWIN0MAP = 0x180,
rWIN1MAP = 0x184,
rWIN2MAP = 0x188,
rWIN3MAP = 0x18C,
rWIN4MAP = 0x190,
//Window Palette Control
rWPALCON = 0x1A0,
//I80/RGB Trigger Control
rTRIGCON = 0x1A4,
//I80 Interface Control for Main/Sub LDI
rI80IFCONA0 = 0x1B0,
rI80IFCONA1 = 0x1B4,
rI80IFCONB0 = 0x1B8,
rI80IFCONB1 = 0x1BC,
//I80 Interface LDI Command Cotrol
rLDI_CMDCON0 = 0x1D0,
rLDI_CMDCON1 = 0x1D4,
//I80 Interface System Command Control
rSIFCCON0 = 0x1E0,
rSIFCCON1 = 0x1E4,
rSIFCCON2 = 0x1E8,
//I80 Interface LDI Command
rLDI_CMD0 = 0x280,
rLDI_CMD1 = 0x284,
rLDI_CMD2 = 0x288,
rLDI_CMD3 = 0x28C,
rLDI_CMD4 = 0x290,
rLDI_CMD5 = 0x294,
rLDI_CMD6 = 0x298,
rLDI_CMD7 = 0x29C,
rLDI_CMD8 = 0x2A0,
rLDI_CMD9 = 0x2A4,
rLDI_CMD10 = 0x2A8,
rLDI_CMD11 = 0x2AC,
//Window Palette Data
rW2PDATA01 = 0x300,
rW2PDATA23 = 0x304,
rW2PDATA45 = 0x308,
rW2PDATA67 = 0x30C,
rW2PDATA89 = 0x310,
rW2PDATAAB = 0x314,
rW2PDATACD = 0x318,
rW2PDATAEF = 0x31C,
rW3PDATA01 = 0x320,
rW3PDATA23 = 0x324,
rW3PDATA45 = 0x328,
rW3PDATA67 = 0x32C,
rW3PDATA89 = 0x330,
rW3PDATAAB = 0x334,
rW3PDATACD = 0x338,
rW3PDATAEF = 0x33C,
rW4PDATA01 = 0x340,
rW4PDATA23 = 0x344,
//Win0 Palette Ram Access Address(not SFR)
W0PRAMSTART = 0x400,
//Win1 Palette Ram Access Address(not SFR)
W1PRAMSTART = 0x800
};
/////////////////////////////////////////////////////
// LCD SFR Write
#define LcdcOutp32(offset, x) Outp32(LCD_BASE+offset, x)
#define LcdcOutp16(offset, x) Outp16(LCD_BASE+offset, x)
#define LCD_DCLK_Lo GPIO_SetDataEach(eGPIO_C, eGPIO_5 , 0); //GPC[5]:SPI_SCLK -> Low
#define LCD_DCLK_Hi GPIO_SetDataEach(eGPIO_C, eGPIO_5 , 1); //GPC[5]:SPI_SCLK -> High
#define LCD_DSERI_Lo GPIO_SetDataEach(eGPIO_C, eGPIO_6 , 0); //GPC[6]:SPI_MOSI -> Low
#define LCD_DSERI_Hi GPIO_SetDataEach(eGPIO_C, eGPIO_6 , 1); //GPC[6]:SPI_MOSI -> High
#define LCD_DEN_Lo GPIO_SetDataEach(eGPIO_C, eGPIO_7 , 0); //GPC[7]:SPI_CS -> Low
#define LCD_DEN_Hi GPIO_SetDataEach(eGPIO_C, eGPIO_7 , 1); //GPC[7]:SPI_CS -> High
// VIDCON0
// MSB or LSB Out in RGB Seiral I/F
#define MSB_OUT_IN_SERIAL (0<<30)
#define LSB_OUT_IN_SERIAL (1<<30)
#define INTERLACE (1<<29)
#define PROGRESSIVE (0<<29)
#define VIDOUT_RGBIF (0<<26)
#define VIDOUT_TV (1<<26)
#define VIDOUT_I80IF0 (2<<26)
#define VIDOUT_I80IF1 (3<<26)
#define VIDOUT_TVNRGBIF (4<<26)
#define VIDOUT_TVNI80IF0 (6<<26)
#define VIDOUT_TVNI80IF1 (7<<26)
#define PNRMODE_RGB_P (0<<17)
#define PNRMODE_BGR_P (1<<17)
#define PNRMODE_RGB_S (2<<17)
#define PNRMODE_BGR_S (3<<17)
#define PNRMODE_MASK (3<<17)
#define CLKVALUP_ALWAYS (0<<16)
#define CLKVALUP_ST_FRM (1<<16)
#define CLKVAL_F(n) (((n)&0xFF)<<6)
#define VCLKEN_DISABLE (1<<5)
#define VCLKEN_ENABLE (0<<5)
#define CLKDIR_F(n) (((n)&0x1)<<4)
#define CLKDIR_DIRECT (0<<4)
#define CLKDIR_DIVIDED (1<<4)
#define CLKDIR_MASK (1<<4)
#define CLKSEL_F_HCLK (0<<2)
#define CLKSEL_F_SYSCON (1<<2)
#define CLKSEL_F_EXTCLK (3<<2)
#define ENVID_DISABLE (0<<1)
#define ENVID_F_DISABLE (0<<0)
// CPU Interface Data Format (MAIN LDI)
#define MAIN_16_MODE (0<<20)
#define MAIN_16PLUS2_MODE (1<<20)
#define MAIN_9PLUS9_MODE (2<<20)
#define MAIN_16PLUS8_MODE (3<<20)
#define MAIN_18_MODE (4<<20)
#define MAIN_8PLUS8_MODE (5<<20)
// CPU Interface Data Format (SUB LDI)
#define SUB_16_MODE (0<<23)
#define SUB_16PLUS2_MODE (1<<23)
#define SUB_9PLUS9_MODE (2<<23)
#define SUB_16PLUS8_MODE (3<<23)
#define SUB_18_MODE (4<<23)
#define SUB_8PLUS8_MODE (5<<23)
// Main Control1 register (VIDCON1)
#define IVCLK_FALL_EDGE (0<<7)
#define IVCLK_RISE_EDGE (1<<7)
#define IHSYNC_NORMAL (0<<6)
#define IHSYNC_INVERT (1<<6)
#define IVSYNC_NORMAL (0<<5)
#define IVSYNC_INVERT (1<<5)
#define IVDEN_NORMAL (0<<4)
#define IVDEN_INVERT (1<<4)
// Time Control0 register (VIDTCON0)
#define VBPDE(n) (((n)&0xFF)<<24)
#define VBPD(n) (((n)&0xFF)<<16)
#define VFPD(n) (((n)&0xFF)<<8)
#define VSPW(n) (((n)&0xFF)<<0)
// Time Control1 register (VIDTCON1)
#define VFPDE(n) (((n)&0xFF)<<24)
#define HBPD(n) (((n)&0xFF)<<16)
#define HFPD(n) (((n)&0xFF)<<8)
#define HSPW(n) (((n)&0xFF)<<0)
// Time Control2 register (VIDTCON2)
#define LINEVAL(n) (((n)&0x7FF)<<11)
#define HOZVAL(n) (((n)&0x7FF)<<0)
// v3.2
#define RSADD4TO1(n) (((n)&0xF)<<23)
// WINCON0 SFR for local path
#define W0DMA (0<<22)
#define W0LOCAL_POST (1<<22)
#define W0ENLOCAL_MASK (1<<22)
// WINCON1 SFR for local path
#define W1DMA (0<<22)
#define W1LOCAL (1<<22)
#define W1ENLOCAL_MASK (1<<22)
#define W1ENLOCAL_CIM (1<<23)
#define W1ENLOCAL_POST (0<<23)
#define W1LOCAL_CIM_MASK (1<<23)
#define W0BUF0 (0<<20)
#define W0BUF1 (1<<20)
#define W0BUF_MASK (1<<20)
#define W0BUFAUTO_DISABLE (0<<19)
#define W0BUFAUTO_ENABLE (1<<19)
#define W0BUFAUTO_MASK (1<<19)
#define IN_LOCAL_RGB (0<<13)
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