?? sromc_test.c
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/**************************************************************************************
*
* Project Name : S3C6400 Validation
*
* Copyright 2006 by Samsung Electronics, Inc.
* All rights reserved.
*
* Project Description :
* This software is only for validating functions of the S3C6400.
* Anybody can use this software without our permission.
*
*--------------------------------------------------------------------------------------
*
* File Name : SROMC_test.c
*
* File Description : This file implements the functons for SROM controller test.
*
* Author : Sunil Roe
* Dept. : AP Development Team
* Created Date : 2007/02/22
* Version : 0.1
*
* History
* - Created(sunil.roe 2007/02/22)
*
**************************************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <ctype.h>
#include "def.h"
#include "option.h"
#include "library.h"
#include "sfr6400.h"
#include "system.h"
#include "sysc.h"
#include "dma.h"
#include "intc.h"
#include "sromc.h"
#include "nand.h"
#include "onenand.h"
#include "cf.h"
#include "ata.h"
#include "timer.h"
#include "am29f800.h"
#include "cs8900.h"
#define SRAM_DATA_SIZE 0x1000
#define NAND_DATA_SIZE NAND_PAGE_512
EBI_oInform g_oaEBIInform[MEMIF_NUM];
u8 aBuffer[NAND_PAGE_MAX];
u8 aSpareBuffer[NAND_SPARE_MAX];
u32 aReadData[ONENAND_PAGESIZE/4] = {0, };
u32 g_uLLIBaseAddr = _DRAM_BaseAddress + 0x00100000;
volatile u32 Nand_DmaTestDone;
u32 g_uOneNANDSrcAddr = 0;
void EBI_Test_Assem(void);
void EBI_Test(void);
void SMC_Test(void);
void SMC_TestATABug(void);
void SMC_TestATAResetBug(void);
void AMD_Test(void)
{
Disp("\n[Check AM29LVxxx]\n");
switch(AM29F800_CheckId())
{
case 1 :
printf("This device is AM29LV200B!\n");
break;
case 2 :
printf("This device is AM29LV400B!\n");
break;
case 3 :
printf("This device is AM29LV800B!\n");
break;
case 4 :
printf("This device is AM29LV160B!\n");
break;
case 5 :
printf("This device is AM29LV320B!\n");
break;
default:
printf("ID Check Error!!!\n");
return;
}
}
/*---------------------------------- ISR Routines ---------------------------------*/
//////////
// Function Name : ISR_EBIDMC0
// Function Description : This function implements the ISR of DMC0's DMA Interrupt.
// Input : NONE
// Output : NONE
// Version : v0.1
void __irq ISR_EBIDMC0(void)
{
Disp("ISR_EBIDMC0\n");
INTC_Disable(g_oaEBIInform[eMEM_DMC0].ucIntNum);
// Interrupt Clear
DMACH_ClearIntPending(&g_oaEBIInform[eMEM_DMC0].oEBIDma);
DMACH_ClearErrIntPending(&g_oaEBIInform[eMEM_DMC0].oEBIDma);
// Channel Set-up
DMACH_Setup( g_oaEBIInform[eMEM_DMC0].eDMACh, 0x0,
g_oaEBIInform[eMEM_DMC0].uSrcAddr, g_oaEBIInform[eMEM_DMC0].bSrcFixed,
g_oaEBIInform[eMEM_DMC0].uDstAddr, g_oaEBIInform[eMEM_DMC0].bDstFixed,
g_oaEBIInform[eMEM_DMC0].eDataSz, g_oaEBIInform[eMEM_DMC0].uDataCnt, DEMAND,
g_oaEBIInform[eMEM_DMC0].eSrcReq, g_oaEBIInform[eMEM_DMC0].eDstReq,
g_oaEBIInform[eMEM_DMC0].eBurstMode, &g_oaEBIInform[eMEM_DMC0].oEBIDma);
DMACH_Start(&g_oaEBIInform[eMEM_DMC0].oEBIDma); // DMA Re-Start
INTC_Enable(g_oaEBIInform[eMEM_DMC0].ucIntNum);
INTC_ClearVectAddr();
}
//////////
// Function Name : ISR_EBISROMC
// Function Description : This function implements the ISR of DMC0's DMA Interrupt.
// Input : NONE
// Output : NONE
// Version : v0.1
void __irq ISR_EBISROMC(void)
{
// Disp("ISR_EBISROMC\n");
INTC_Disable(g_oaEBIInform[eMEM_SROMC].ucIntNum);
// Interrupt Clear
DMACH_ClearIntPending(&g_oaEBIInform[eMEM_SROMC].oEBIDma);
DMACH_ClearErrIntPending(&g_oaEBIInform[eMEM_SROMC].oEBIDma);
if (CompareDMA(g_oaEBIInform[eMEM_SROMC].uSrcAddr, g_oaEBIInform[eMEM_SROMC].uDstAddr, (DATA_SIZE)WORD, SRAM_DATA_SIZE-1))
{
// Disp(" >> Test Tx&Rx -> Ok << \n");
Disp("!");
// Channel Set-up
DMACH_Setup( g_oaEBIInform[eMEM_SROMC].eDMACh, 0x0,
g_oaEBIInform[eMEM_SROMC].uSrcAddr, g_oaEBIInform[eMEM_SROMC].bSrcFixed,
g_oaEBIInform[eMEM_SROMC].uDstAddr, g_oaEBIInform[eMEM_SROMC].bDstFixed,
g_oaEBIInform[eMEM_SROMC].eDataSz, g_oaEBIInform[eMEM_SROMC].uDataCnt, DEMAND,
g_oaEBIInform[eMEM_SROMC].eSrcReq, g_oaEBIInform[eMEM_SROMC].eDstReq,
g_oaEBIInform[eMEM_SROMC].eBurstMode, &g_oaEBIInform[eMEM_SROMC].oEBIDma);
DMACH_Start(&g_oaEBIInform[eMEM_SROMC].oEBIDma); // DMA Re-Start
INTC_Enable(g_oaEBIInform[eMEM_SROMC].ucIntNum);
INTC_ClearVectAddr();
}
else
{
Disp(" >>*** Tx-data & Rx-data mismatch ***<< \n");
}
}
//////////
// Function Name : ISR_EBINAND
// Function Description : This function implements the ISR of NAND's DMA Interrupt.
// Input : NONE
// Output : NONE
// Version : v0.1
void __irq ISR_EBINAND(void)
{
Disp("N ");
INTC_Disable(g_oaEBIInform[eMEM_NAND].ucIntNum);
// Interrupt Clear
DMACH_ClearIntPending(&g_oaEBIInform[eMEM_NAND].oEBIDma);
DMACH_ClearErrIntPending(&g_oaEBIInform[eMEM_NAND].oEBIDma);
// Channel Set-up
DMACH_Setup( g_oaEBIInform[eMEM_NAND].eDMACh, 0x0,
g_oaEBIInform[eMEM_NAND].uSrcAddr, g_oaEBIInform[eMEM_NAND].bSrcFixed,
g_oaEBIInform[eMEM_NAND].uDstAddr, g_oaEBIInform[eMEM_NAND].bDstFixed,
g_oaEBIInform[eMEM_NAND].eDataSz, g_oaEBIInform[eMEM_NAND].uDataCnt, DEMAND,
g_oaEBIInform[eMEM_NAND].eSrcReq, g_oaEBIInform[eMEM_NAND].eDstReq,
g_oaEBIInform[eMEM_NAND].eBurstMode, &g_oaEBIInform[eMEM_NAND].oEBIDma);
NAND_ReadPageSLCSetup(0, 50, 0);
DMACH_Start(&g_oaEBIInform[eMEM_NAND].oEBIDma); // DMA Re-Start
INTC_Enable(g_oaEBIInform[eMEM_NAND].ucIntNum);
INTC_ClearVectAddr();
// DelayfrTimer(milli, 1);
}
//////////
// Function Name : ISR_EBINANDLLI
// Function Description : This function implements the ISR of NAND's DMA Interrupt.
// Input : NONE
// Output : NONE
// Version : v0.1
void __irq ISR_EBINANDLLI(void)
{
INTC_Disable(g_oaEBIInform[eMEM_NAND].ucIntNum);
Disp(".");
// NAND_WritePageSLCClose(0, aSpareBuffer);
// Interrupt Clear
DMACH_ClearIntPending(&g_oaEBIInform[eMEM_NAND].oEBIDma);
DMACH_ClearErrIntPending(&g_oaEBIInform[eMEM_NAND].oEBIDma);
Nand_DmaTestDone++;
INTC_Enable(g_oaEBIInform[eMEM_NAND].ucIntNum);
INTC_ClearVectAddr();
}
//////////
// Function Name : ISR_EBIOneNAND
// Function Description : This function implements the ISR of OneNAND's DMA Interrupt.
// Input : NONE
// Output : NONE
// Version : v0.1
void __irq ISR_EBIOneNAND(void)
{
Disp("ISR_EBIOneNAND\n");
INTC_Disable(g_oaEBIInform[eMEM_OneNAND].ucIntNum);
// Interrupt Clear
DMACH_ClearIntPending(&g_oaEBIInform[eMEM_OneNAND].oEBIDma);
DMACH_ClearErrIntPending(&g_oaEBIInform[eMEM_OneNAND].oEBIDma);
// Channel Set-up
DMACH_Setup( g_oaEBIInform[eMEM_OneNAND].eDMACh, 0x0,
g_oaEBIInform[eMEM_OneNAND].uSrcAddr, g_oaEBIInform[eMEM_OneNAND].bSrcFixed,
g_oaEBIInform[eMEM_OneNAND].uDstAddr, g_oaEBIInform[eMEM_OneNAND].bDstFixed,
g_oaEBIInform[eMEM_OneNAND].eDataSz, g_oaEBIInform[eMEM_OneNAND].uDataCnt, DEMAND,
g_oaEBIInform[eMEM_OneNAND].eSrcReq, g_oaEBIInform[eMEM_OneNAND].eDstReq,
g_oaEBIInform[eMEM_OneNAND].eBurstMode, &g_oaEBIInform[eMEM_OneNAND].oEBIDma);
NAND_ReadPageSLCSetup(0, 50, 0);
DMACH_Start(&g_oaEBIInform[eMEM_OneNAND].oEBIDma); // DMA Re-Start
INTC_Enable(g_oaEBIInform[eMEM_OneNAND].ucIntNum);
INTC_ClearVectAddr();
// DelayfrTimer(milli, 1);
}
void EBI_SetDMAParams(Mem_eType eMemType)
{
u32 uLoopCnt = 0;
u32 uTotTxferBytes = 0;
s32 iBankSel = 0;
//------- Init DMA params
switch(eMemType)
{
case eMEM_DMC0 :
Disp("Selected DMAC 0 ..... \n");
g_oaEBIInform[eMemType].ucIntNum = NUM_DMA0;
g_oaEBIInform[eMemType].eDMACon = DMA0;
g_oaEBIInform[eMemType].eDMACh = DMA_A;
g_oaEBIInform[eMemType].uSrcAddr = _DRAM_BaseAddress + 0x01000000;
g_oaEBIInform[eMemType].uDstAddr = _DRAM_BaseAddress + 0x04000000;
g_oaEBIInform[eMemType].bSrcFixed = eINCREMENT;
g_oaEBIInform[eMemType].bDstFixed = eINCREMENT;
g_oaEBIInform[eMemType].eDataSz = WORD; // Set DMA Data Width
g_oaEBIInform[eMemType].uDataCnt = 0x10000; // Set DMA Transfer Count
g_oaEBIInform[eMemType].eSrcReq = MEM;
g_oaEBIInform[eMemType].eDstReq = MEM;
g_oaEBIInform[eMemType].eBurstMode = SINGLE;
g_oaEBIInform[eMemType].pHandler = ISR_EBIDMC0;
uTotTxferBytes = g_oaEBIInform[eMemType].uDataCnt * g_oaEBIInform[eMemType].eDataSz;
// 0. Clear the rx buf.
for (uLoopCnt = 0; uLoopCnt<uTotTxferBytes; uLoopCnt++)
*(u8 *)(g_oaEBIInform[eMemType].uDstAddr+uLoopCnt) = 0;
// 1. Set up the tx buf.
for (uLoopCnt = 0; uLoopCnt<uTotTxferBytes; uLoopCnt++)
*(u8 *)(g_oaEBIInform[eMemType].uSrcAddr+uLoopCnt) = (u8)(uLoopCnt+2)%0xff;
break;
case eMEM_NAND :
g_oaEBIInform[eMemType].ucIntNum = NUM_DMA1;
g_oaEBIInform[eMemType].eDMACon = DMA1;
g_oaEBIInform[eMemType].eDMACh = DMA_A;
// g_oaEBIInform[eMemType].uLLIBaseAddr = 0x0;
g_oaEBIInform[eMemType].uLLIBaseAddr = g_uLLIBaseAddr+0x20;
g_oaEBIInform[eMemType].uSrcAddr = 0x52000000;
g_oaEBIInform[eMemType].uDstAddr = (u32)(NFCON_BASE + 0x10); // NFDATA register address
g_oaEBIInform[eMemType].bSrcFixed = eINCREMENT;
g_oaEBIInform[eMemType].bDstFixed = eFIX;
g_oaEBIInform[eMemType].eDataSz = WORD; // Set DMA Data Width
// g_oaEBIInform[eMemType].uDataCnt = NAND_DATA_SIZE; // Set DMA Transfer Count
g_oaEBIInform[eMemType].uDataCnt = 64; // Set DMA Transfer Count
g_oaEBIInform[eMemType].eSrcReq = MEM;
g_oaEBIInform[eMemType].eDstReq = DMA1_NAND_RX;
g_oaEBIInform[eMemType].eBurstMode = SINGLE;
// g_oaEBIInform[eMemType].eBurstMode = BURST128;
g_oaEBIInform[eMemType].pHandler = ISR_EBINANDLLI;
break;
case eMEM_SROMC :
Disp("Selected SDMAC 0 ..... \n");
Disp("0)nCS0 1)nCS1 4)nCS4 5)nCS5\n");
Disp("\nSelect SROM Bank(\"0\" to exit) : ");
iBankSel = GetIntNum();
if( (iBankSel < 0) || (iBankSel == 2) || (iBankSel == 3) || (iBankSel > 5))
return; // return.
SROMC_SetBank((u8)iBankSel, eEn_CTL, eEn_WAIT, e16bit, eNor_Mode, (Bank_eTiming)0, (Bank_eTiming)3, (Bank_eTiming)20, (Bank_eTiming)0, (Bank_eTiming)0, (Bank_eTiming)2);
g_oaEBIInform[eMemType].ucIntNum = NUM_SDMA0;
g_oaEBIInform[eMemType].eDMACon = SDMA0;
g_oaEBIInform[eMemType].eDMACh = DMA_A;
g_oaEBIInform[eMemType].uSrcAddr = _SMC_BaseAddress + 0x08000000*iBankSel;
g_oaEBIInform[eMemType].uDstAddr = _DRAM_BaseAddress + 0x04000000;
g_oaEBIInform[eMemType].bSrcFixed = eINCREMENT;
g_oaEBIInform[eMemType].bDstFixed = eINCREMENT;
g_oaEBIInform[eMemType].eDataSz = WORD; // Set DMA Data Width
g_oaEBIInform[eMemType].uDataCnt = SRAM_DATA_SIZE; // Set DMA Transfer Count
g_oaEBIInform[eMemType].eSrcReq = MEM;
g_oaEBIInform[eMemType].eDstReq = MEM;
g_oaEBIInform[eMemType].eBurstMode = SINGLE;
g_oaEBIInform[eMemType].pHandler = ISR_EBISROMC;
uTotTxferBytes = g_oaEBIInform[eMemType].uDataCnt * g_oaEBIInform[eMemType].eDataSz;
// 0. Clear the rx buf.
for (uLoopCnt = 0; uLoopCnt<uTotTxferBytes; uLoopCnt++)
*(u8 *)(g_oaEBIInform[eMemType].uDstAddr+uLoopCnt) = 0;
// 1. Set up the tx buf.
for (uLoopCnt = 0; uLoopCnt<uTotTxferBytes; uLoopCnt++)
*(u8 *)(g_oaEBIInform[eMemType].uSrcAddr+uLoopCnt) = (u8)(uLoopCnt+2)%0xff;
break;
case eMEM_OneNAND :
Disp("Selected SDMAC 1 ..... \n");
g_oaEBIInform[eMemType].ucIntNum = NUM_SDMA1;
g_oaEBIInform[eMemType].eDMACon = SDMA1;
g_oaEBIInform[eMemType].eDMACh = DMA_A;
g_oaEBIInform[eMemType].uSrcAddr = g_uOneNANDSrcAddr; // NFDATA register address
g_oaEBIInform[eMemType].uDstAddr = (u32)aReadData;
g_oaEBIInform[eMemType].bSrcFixed = eFIX;
g_oaEBIInform[eMemType].bDstFixed = eINCREMENT;
g_oaEBIInform[eMemType].eDataSz = WORD; // Set DMA Data Width
g_oaEBIInform[eMemType].uDataCnt = ONENAND_PAGESIZE/4; // Set DMA Transfer Count
g_oaEBIInform[eMemType].eSrcReq = MEM;
g_oaEBIInform[eMemType].eDstReq = MEM;
g_oaEBIInform[eMemType].eBurstMode = BURST128;
g_oaEBIInform[eMemType].pHandler = ISR_EBIOneNAND;
uTotTxferBytes = g_oaEBIInform[eMemType].uDataCnt * g_oaEBIInform[eMemType].eDataSz;
// 0. Clear the rx buf.
// for (uLoopCnt = 0; uLoopCnt<uTotTxferBytes; uLoopCnt++)
// *(u8 *)(g_oaEBIInform[eMemType].uDstAddr+uLoopCnt) = 0;
// 1. Set up the tx buf.
for (uLoopCnt = 0; uLoopCnt<uTotTxferBytes; uLoopCnt++)
*(u8 *)(g_oaEBIInform[eMemType].uSrcAddr+uLoopCnt) = (u8)(uLoopCnt+2)%0xff;
break;
}
DMAC_InitCh(g_oaEBIInform[eMemType].eDMACon, g_oaEBIInform[eMemType].eDMACh, &g_oaEBIInform[eMemType].oEBIDma);
INTC_SetVectAddr(g_oaEBIInform[eMemType].ucIntNum, g_oaEBIInform[eMemType].pHandler);
INTC_Enable(g_oaEBIInform[eMemType].ucIntNum);
// Channel, LLI_Address, SrcAddr, Src Type, DstAddr, Dst Type, Transfer Width, Transfer Size, OpMode(DEMAND), Src Req, Dst Req, Burst
// Channel Set-up
DMACH_Setup( g_oaEBIInform[eMemType].eDMACh, g_oaEBIInform[eMemType].uLLIBaseAddr,
g_oaEBIInform[eMemType].uSrcAddr, g_oaEBIInform[eMemType].bSrcFixed,
g_oaEBIInform[eMemType].uDstAddr, g_oaEBIInform[eMemType].bDstFixed,
g_oaEBIInform[eMemType].eDataSz, g_oaEBIInform[eMemType].uDataCnt, DEMAND,
g_oaEBIInform[eMemType].eSrcReq, g_oaEBIInform[eMemType].eDstReq,
g_oaEBIInform[eMemType].eBurstMode, &g_oaEBIInform[eMemType].oEBIDma);
}
void EBI_CloseDMA(Mem_eType eMemType)
{
INTC_Disable(g_oaEBIInform[eMemType].ucIntNum);
DMAC_Close(g_oaEBIInform[eMemType].eDMACon, g_oaEBIInform[eMemType].eDMACh, &g_oaEBIInform[eMemType].oEBIDma);
}
void SRAM_Test(void)
{
u32 uLoopCnt = 0;
u32 uTempAddr = 0;
// SYSC_CtrlEBIPrio(eEBI_FIX4);
#if 1
EBI_SetDMAParams(eMEM_SROMC);
//-------- SRAM setting --------------
uTempAddr = g_oaEBIInform[eMEM_SROMC].uDstAddr;
for(uLoopCnt=0 ; uLoopCnt<SRAM_DATA_SIZE ; uLoopCnt++)
{
*(volatile u32*)(uTempAddr) = 0;
uTempAddr += 4;
}
Disp("* Source Buffer Address : 0x%x\n", g_oaEBIInform[eMEM_SROMC].uSrcAddr);
Disp("* Destination Buffer Address : 0x%x\n", g_oaEBIInform[eMEM_SROMC].uDstAddr);
Disp("If you want to exit, Press the 'x' key.\n");
// Enable DMAs
DMACH_Start(&g_oaEBIInform[eMEM_SROMC].oEBIDma); // SROMC DMA Start
#endif
while(1)
{
if(Getc()=='x')
{
break;
}
}
EBI_CloseDMA(eMEM_SROMC);
}
#define SMC_NAND_DMA_TEST 1
#define SMC_SRAM_DMA_TEST 1
#define SMC_UDMA_TEST 1
//////////
// Function Name : SMC_TestEBIUsingNAND
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