?? sysc.c
字號:
}
else // ASync Mode
{
uRegValue_M = (u32)(((u32)(0x1<<31))|(uMVAL_M<<16)|(uPVAL_M<<8)|(uSVAL_M<<0));
//uRegValue_E = Inp32(rEPLL_CON0);
}
// Divider Change
uRegValue = Inp32(rCLK_DIV0);
uRegValue = (uRegValue & ~(0xFE07)) | ((uPCLK_Ratio<<12)|(uHCLKx2_Ratio<<9)|(uARM_Ratio<<0));
Outp32(rCLK_DIV0, uRegValue);
#if 0
// EVT0 W.A
Outp32(rMPLL_CON, uRegValue_M);
if(uTemp == 0)
{
Outp32(rEPLL_CON0, uRegValue_E);
}
// APLL Set
#endif
Outp32(rAPLL_CON, uRegValue_A);
Delay(10);
Outp32(rMPLL_CON, uRegValue_M);
Delay(10);
SYSC_GetClkInform();
UART_InitDebugCh(0, 115200);
Delay(10);
printf("============================ \n");
printf("Current Clock Information \n");
printf("ARMCLK: %.2fMHz HCLKx2: %.2fMHz HCLK: %.2fMHz PCLK: %.2fMHz\n",(float)g_ARMCLK/1.0e6, (float)g_HCLKx2/1.0e6, (float)g_HCLK/1.0e6, (float)g_PCLK/1.0e6);
printf("============================ \n");
}
//////////
// Function Name : SYSC_ChangeSYSCLK_1
// Function Description : This function control System Clock
// Fout = (mdiv * Fin) / (pdiv x 2^sdiv), Fout = ((mdiv+k/2^16) * Fin) / (pdiv x 2^sdiv)
// Input : eAPLLMPS : APLL M,P,S Value
// eMPLLMPS : MPLL M,P,S Value ( using at Async Mode )
// uARM_Ratio : ARM Divider
// uHCLKx2_Ratio : HCLKx2 Divider
// uPCLK_Ratio : PCLK Divider
// Other values are retained
// Output : NONE
// Version :
void SYSC_ChangeSYSCLK_1(APLL_eOUT eAPLLMPS, APLL_eOUT eMPLLMPS, u32 uARM_Ratio, u32 uHCLKx2_Ratio, u32 uPCLK_Ratio)
{
u32 uRegValue_A;
u32 uRegValue_M;//, uRegValue_E;
u32 uMVAL, uPVAL, uSVAL;
u32 uMVAL_M, uPVAL_M, uSVAL_M;
u32 uSYNCMODE;
u32 uRegValue_DIV0, uRegValue_SRC, uTemp, uTemp1;
uMVAL = (eAPLLMPS&0x3FF0000)>>16;
uPVAL = (eAPLLMPS&0xFF00)>>8;
uSVAL = eAPLLMPS&0x00FF;
uRegValue_A = (u32)(((u32)(0x1<<31))|(uMVAL<<16)|(uPVAL<<8)|(uSVAL<<0));
uMVAL_M = (eMPLLMPS&0x3FF0000)>>16;
uPVAL_M = (eMPLLMPS&0xFF00)>>8;
uSVAL_M = eMPLLMPS&0x00FF;
uSYNCMODE = (Inp32(rOTHERS)>>8)&0xF;
if(uSYNCMODE==0xF ) // Sync Mode
{
uRegValue_M = Inp32(rMPLL_CON);
}
else // ASync Mode
{
uRegValue_M = (u32)(((u32)(0x1<<31))|(uMVAL_M<<16)|(uPVAL_M<<8)|(uSVAL_M<<0));
//uRegValue_E = Inp32(rEPLL_CON0);
}
// Clock Divider Change 1:2:2
uRegValue_DIV0 = Inp32(rCLK_DIV0);
uTemp = (uRegValue_DIV0&~(0xFFFF))|(1<<12)|((0<<9)|(1<<8)|(1<<4)|(0<<0)); // ARM:HCLKx2:HCLK:PCLK = 1:1:2:2
// Set-up Divider Value
uRegValue_DIV0 = (uRegValue_DIV0 & ~(0xFE07)) | ((uPCLK_Ratio<<12)|(uHCLKx2_Ratio<<9)|(uARM_Ratio<<0));
uRegValue_SRC = Inp32(rCLK_SRC);
uTemp1 = (uRegValue_SRC&~(0x7))|0x0;
Outp32(rCLK_SRC, uTemp1); // Clock Source Change
Outp32(rCLK_DIV0, uTemp); // Change Clock Divider
// PLL Change
if(uSYNCMODE == 0)
{
Outp32(rMPLL_CON, uRegValue_M);
}
Outp32(rAPLL_CON, uRegValue_A);
while(((Inp32(rAPLL_CON)>>30)&0x1)==0);
// Change Divider Value
Outp32(rCLK_DIV0, uRegValue_DIV0);
// Change Clock SRC
Outp32(rCLK_SRC, uRegValue_SRC);
SYSC_GetClkInform();
UART_InitDebugCh(0, 115200);
Delay(10);
printf("============================ \n");
printf("Current Clock Information \n");
printf("ARMCLK: %.2fMHz HCLKx2: %.2fMHz HCLK: %.2fMHz PCLK: %.2fMHz\n",(float)g_ARMCLK/1.0e6, (float)g_HCLKx2/1.0e6, (float)g_HCLK/1.0e6, (float)g_PCLK/1.0e6);
printf("============================ \n");
}
#define uTIME_OF_XTAL (1.0e6/(float)FIN)
//////////
// Function Name : SYSC_SetLockTime
// Function Description : This function control APLL Lock Time (PLL9025X), Max 100us
// Fout = (mdiv * Fin) / (pdiv x 2^sdiv)
// Input : uLockTime : Max 100us, us order
// ePLL : PLL Type
// Output : NONE
// Version :
void SYSC_SetLockTime( PLL_eTYPE ePLL, u32 uLockTime)
{
u32 uLockCount;
uLockCount = (unsigned int)((float)uLockTime/((float)uTIME_OF_XTAL));
printf("uLockCount : 0x%x\n", uLockCount);
switch(ePLL)
{
case eAPLL:
Outp32(rAPLL_LOCK, uLockCount); break;
case eMPLL:
Outp32(rMPLL_LOCK, uLockCount); break;
case eEPLL:
Outp32(rEPLL_LOCK, uLockCount); break;
}
}
//////////
// Function Name : SYSC_ClkSrc
// Function Description : This function select Clock Source
//
// Input : CLKSRC_eId
// Output : NONE
// Version :
void SYSC_ClkSrc( CLKSRC_eId eClkSrc)
{
u32 uCtrl, uOffset, uFuct;
u32 uRegValue;
uCtrl = (eClkSrc&0xF000)>>12;
uOffset = (eClkSrc&0x0FF0)>>4;
uFuct = eClkSrc&0x000F;
uRegValue = Inp32(rCLK_SRC);
uRegValue = (uRegValue & ~(uCtrl<<(uOffset))) | (uFuct<<(uOffset));
Outp32(rCLK_SRC, uRegValue);
}
//////////
// Function Name : SYSC_SetDIV0
// Function Description : This function set Clock divider0 register ratio
//
// Input : uAratio : DIV_APLL ( 0 ~ 15)
// uMratio : DIV_MPLL ( 0~1)
// uHratio : DIV_HCLK (0~1), HCLKx2
// uHx2ratio: DIV_HCLKx2(0~7), (APLL or MPLL)
// uPratio : DIV_PCLK (0~15), HCLKx2
// uONDratio: DIV_ONDCLK(0~3), HCLKx2
// uSECUratio:DIV_Security(0~3), HCLKx2
// uCAMratio: DIV_CAM(0~15), HCLKx2
// uJPEGratio: DIV_JPEG(0~15), HCLKx2
// uMFCratio: DIV_MFC(0~15), HCLKx2
// Output : NONE
// Version :
void SYSC_SetDIV0( u32 uAratio, u32 uMratio, u32 uHratio, u32 uHx2ratio, u32 uPratio,
u32 uONDratio, u32 uSECUratio, u32 uCAMratio, u32 uJPEGratio, u32 uMFCratio )
{
u32 uRegValue;
uRegValue =
( (uMFCratio<<28)| // HCLKx2/(uMFCratio + 1)
(uJPEGratio<<24) | // HCLKx2/(uJPEGratio + 1)
(uCAMratio<<20) | // HCLKx2/(uCAMratio + 1)
(uSECUratio<<18)| // HCLKx2/(uSECUratio + 1)
(uONDratio<<16) | // HCLKx2/(uONDratio +1 )
(uPratio<<12) | // HCLKx2/(uPratio+1)
(uHx2ratio<<9) |
(uHratio<<8)| // HCLKx2(uHratio+1)
(uMratio<<4)|
(uAratio<<0)) ;
Outp32(rCLK_DIV0, uRegValue);
}
//////////
// Function Name : SYSC_SetDIV0_all
// Function Description : This function set Clock divider0 register ratio
// Input : None
// Version :
// add by rb1004
void SYSC_SetDIV0_all(u32 uSetRatio)
{
Outp32(rCLK_DIV0, uSetRatio);
}
//////////
// Function Name : SYSC_GetDIV0
// Function Description : This function get Clock divider0 register ratio
// Input : None
// Version :
// add by rb1004
u32 SYSC_GetDIV0( void)
{
return Inp32(rCLK_DIV0);
}
//////////
// Function Name : SYSC_SetDIV1
// Function Description : This function set Clock divider1 register ratio
//
// Input : uMMC0ratio : (0~15)
// uMMC1ratio : (0~15)
// uMMC2ratio : (0~15)
// uLCDratio : (0~15)
// uSCALERratio : (0~15)
// uHOSTratio : (0~15)
// Output : NONE
// Version :
void SYSC_SetDIV1( u32 uMMC0ratio, u32 uMMC1ratio, u32 uMMC2ratio, u32 uLCDratio, u32 uSCALERratio, u32 uHOSTratio)
{
u32 uRegValue;
uRegValue =
((uHOSTratio<<20) |
(uSCALERratio<<16) |
(uLCDratio<<12) |
(uMMC2ratio<<8)|
(uMMC1ratio<<4)|
(uMMC0ratio<<0)) ;
Outp32(rCLK_DIV1, uRegValue);
}
//////////
// Function Name : SYSC_SetDIV2
// Function Description : This function set Clock divider2 register ratio
//
// Input : uSPI0ratio : (0~15)
// uSPI1ratio : (0~15)
// uAUDIO0ratio : (0~15)
// uAUDIO1ratio : (0~15)
// uUARTratio : (0~15)
// uIRDAratio : (0~15)
// Output : NONE
// Version :
void SYSC_SetDIV2( u32 uSPI0ratio , u32 uSPI1ratio, u32 uAUDIO0ratio, u32 uAUDIO1ratio, u32 uUARTratio, u32 uIRDAratio)
{
u32 uRegValue;
uRegValue =
((uIRDAratio<<20) |
(uUARTratio<<16) |
(uAUDIO1ratio<<12) |
(uAUDIO0ratio<<8)|
(uSPI1ratio<<4)|
(uSPI0ratio<<0)) ;
Outp32(rCLK_DIV2, uRegValue);
}
//////////
// Function Name : SYSC_CtrlHCLKGate
// Function Description : This function control HCLK_GATE Register
//
// Input : H_eGATE
// uCtrl : Enable_CLK : (1),
// Disable_CLK : (0)
// Output : NONE
// Version :
void SYSC_CtrlHCLKGate( H_eGATE eHCLKGATE , u32 uCtrl)
{
u32 uRegValue, uTemp;
uTemp = eHCLKGATE;
uRegValue =Inp32(rHCLK_GATE);
uRegValue = (uRegValue & ~(0x1<<(uTemp))) | (uCtrl<<(uTemp));
Outp32(rHCLK_GATE, uRegValue);
}
//////////
// Function Name : SYSC_CtrlPCLKGate
// Function Description : This function control PCLK_GATE Register
//
// Input : P_eGATE
// uCtrl : Enable_CLK : (1),
// Disable_CLK : (0)
// Output : NONE
// Version :
void SYSC_CtrlPCLKGate( P_eGATE ePCLKGATE , u32 uCtrl)
{
u32 uRegValue, uTemp;
uTemp = ePCLKGATE;
uRegValue =Inp32(rPCLK_GATE);
uRegValue = (uRegValue & ~(0x1<<(uTemp))) | (uCtrl<<(uTemp));
Outp32(rPCLK_GATE, uRegValue);
}
//////////
// Function Name : SYSC_CtrlSCLKGate
// Function Description : This function control SCLK_GATE Register
//
// Input : S_eGATE
// uCtrl : Enable_CLK : (1),
// Disable_CLK : (0)
// Output : NONE
// Version :
void SYSC_CtrlSCLKGate( S_eGATE eSCLKGATE , u32 uCtrl)
{
u32 uRegValue, uTemp;
uTemp = eSCLKGATE;
uRegValue =Inp32(rSCLK_GATE);
uRegValue = (uRegValue & ~(0x1<<(uTemp))) | (uCtrl<<(uTemp));
Outp32(rSCLK_GATE, uRegValue);
}
//////////
// Function Name : SYSC_CtrlCLKOUT
// Function Description : This function select CLK output
//
// Input : CLKOUT_eTYPE : FOUT_APLL, FOUT_EPLL, HCLK, CLK27M, CLK48M, RTC, Tick, DOUT
// uDivVAL : (0~15)
//
// Output : NONE
// Version :
void SYSC_CtrlCLKOUT( CLKOUT_eTYPE eCLKOUT_TYPE, u32 uDivVAL)
{
u32 uRegValue;
u32 uFunct;
GPIO_SetFunctionEach(eGPIO_F, eGPIO_14, 3); // Select GPIO_SELECT
GPIO_SetPullUpDownEach(eGPIO_F, eGPIO_14, 0);
uFunct = eCLKOUT_TYPE;
uRegValue =Inp32(rCLK_OUT);
uRegValue = (uRegValue & ~(0xFF<<12)) | ((uFunct<<12)|(uDivVAL<<16));
Outp32(rCLK_OUT, uRegValue);
}
//////////
// Function Name : SYSC_CtrlDCLK
// Function Description : This function control DCLK output
//
// Input : uDCLKCMP :(0~15) DCLK compare value, clock toggle value,
// uDCLKDIV : (0~15) DCLK divid value, F_DCLK= Src_CLK/(uDCLKDIV+1)
// uDCLKSEL : "0" PCLK, "1" 48MHz
// uDCLKEN : Enable_CLK : (1),
// Disable_CLK : (0)
// Output : NONE
// Version :
void SYSC_CtrlDCLK( u32 uDCLKCMP, u32 uDCLKDIV, u32 uDCLKSEL, u32 uDCLKEN)
{
u32 uRegValue;
uRegValue =Inp32(rCLK_OUT);
uRegValue = (uRegValue & ~(0xFFF<<0)) | ((uDCLKCMP<<8)|(uDCLKDIV<<4)|(uDCLKSEL<<1)|(uDCLKEN<<0));
Outp32(rCLK_OUT, uRegValue);
}
// Value & 0xF00 : The BUS Control Register ID, OffSet
// Value & 0x0F0 : The BUS Priority Type ID
// Value & 0x00F : The Fixed Priority Order
//////////
// Function Name : SYSC_CtrlBUSPrio
// Function Description : This function control AHB Bus Priority
//
// Input : BUSCTRL_eId
// Output : NONE
// Version :
void SYSC_CtrlBUSPrio( BUSCTRL_eId eBusId)
{
u32 uOffset, uPType, uForder, uOffset1;
u32 uRegValue;
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