?? stm32_init.c
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// <i> Default: One pulse mode disabled
// <o8.2> TIM1_CR1.URS: Update request source
// <i> Default: URS = Counter over-/underflow, UG bit, Slave mode controller
// <0=> Counter over-/underflow, UG bit, Slave mode controller
// <1=> Counter over-/underflow
// <o8.1> TIM1_CR1.UDIS: Update disable
// <i> Default: Update enabled
// </h>
//
// <h> Timer 1 Control Register 2 Configuration (TIM1_CR2)
// <o9.14> TIM1_CR2.OIS4: Output Idle state4 (OC4 output) <0-1>
// <o9.13> TIM1_CR2.OIS3N: Output Idle state3 (OC3N output) <0-1>
// <o9.12> TIM1_CR2.OIS3: Output Idle state3 (OC3 output) <0-1>
// <o9.11> TIM1_CR2.OIS2N: Output Idle state2 (OC2N output) <0-1>
// <o9.10> TIM1_CR2.OIS2: Output Idle state2 (OC2 output) <0-1>
// <o9.9> TIM1_CR2.OIS1N: Output Idle state1 (OC1N output)
// <i> Default: OC1 = 0
// <0=> OC1N=0 when MOE=0
// <1=> OC1N=1 when MOE=0
// <o9.8> TIM1_CR2.OI1S: Output Idle state1 (OC1 output)
// <i> Default: OC1=0
// <0=> OC1=0 when MOE=0
// <1=> OC1=1 when MOE=0
// <o9.7> TIM1_CR2.TI1S: TI1 Selection
// <i> Default: TIM1CH1 connected to TI1 input
// <0=> TIM1CH1 connected to TI1 input
// <1=> TIM1CH1,CH2,CH3 connected to TI1 input
// <o9.4..6> TIM1_CR2.MMS: Master Mode Selection
// <i> Default: Reset
// <i> Select information to be sent in master mode to slave timers for synchronisation
// <0=> Reset
// <1=> Enable
// <2=> Update
// <3=> Compare Pulse
// <4=> Compare OC1REF iused as TRGO
// <5=> Compare OC2REF iused as TRGO
// <6=> Compare OC3REF iused as TRGO
// <7=> Compare OC4REF iused as TRGO
// <o9.2> TIM1_CR2.CCUS: Capture/Compare Control Update Selection
// <i> Default: setting COM bit
// <0=> setting COM bit
// <1=> setting COM bit or rising edge TRGI
// <o9.0> TIM1_CR2.CCPC: Capture/Compare Preloaded Control
// <i> Default: CCxE,CCxNE,OCxM not preloaded
// <0=> CCxE,CCxNE,OCxM not preloaded
// <1=> CCxE,CCxNE,OCxM preloaded
// </h>
//
// <h> Timer 1 Slave mode control register Configuration (TIM1_SMC)
// <o10.15> TIM1_SMCR.ETP: External trigger polarity
// <i> Default: ETR is non-inverted
// <0=> ETR is non-inverted
// <1=> ETR is inverted
// <o10.14> TIM1_SMCR.ECE: External clock mode 2 enabled
// <o10.12..13> TIM1_SMCR.ETPS: External trigger prescaler
// <i> Default: Prescaler OFF
// <0=> Prescaler OFF
// <1=> fETPR/2
// <2=> fETPR/4
// <3=> fETPR/8
// <o10.8..11> TIM1_SMCR.ETF: External trigger filter
// <i> Default: No filter
// <0=> No filter
// <1=> fSampling=fCK_INT, N=2
// <2=> fSampling=fCK_INT, N=4
// <3=> fSampling=fCK_INT, N=8
// <4=> fSampling=fDTS/2, N=6
// <5=> fSampling=fDTS/2, N=8
// <6=> fSampling=fDTS/4, N=6
// <7=> fSampling=fDTS/4, N=8
// <8=> fSampling=fDTS/8, N=6
// <9=> fSampling=fDTS/8, N=8
// <10=> fSampling=fDTS/16, N=5
// <11=> fSampling=fDTS/16, N=6
// <12=> fSampling=fDTS/16, N=8
// <13=> fSampling=fDTS/32, N=5
// <14=> fSampling=fDTS/32, N=6
// <15=> fSampling=fDTS/32, N=8
// <o10.7> TIM1_SMCR.MSM: Delay trigger input
// <o10.4..6> TIM1_SMCR.TS: Trigger Selection
// <i> Default: Reserved
// <0=> Reserved
// <1=> TIM2 (ITR1)
// <2=> TIM3 (ITR2)
// <3=> TIM4 (ITR3)
// <4=> TI1 Edge Detector (TI1F_ED)
// <5=> Filtered Timer Input 1 (TI1FP1)
// <6=> Filtered Timer Input 2 (TI1FP2)
// <7=> External Trigger Input (ETRF)
// <o10.0..2> TIM1_SMCR.SMS: Slave mode selection
// <i> Default: Slave mode disabled
// <0=> Slave mode disabled
// <1=> Encoder mode 1
// <2=> Encoder mode 2
// <3=> Encoder mode 3
// <4=> Reset mode
// <5=> Gated mode
// <6=> Trigger mode
// <7=> External clock mode 1
// </h>
//
//--------------------------------------------------------------------------- Timer 1 channel 1
// <h> Channel 1 Configuration
// <h> Cannel configured as output
// <o11.7> TIM1_CCMR1.OC1CE: Output Compare 1 Clear enabled
// <o11.4..6> TIM1_CCMR1.OC1M: Output Compare 1 Mode
// <i> Default: Frozen
// <0=> Frozen
// <1=> Set channel 1 to active level on match
// <2=> Set channel 1 to inactive level on match
// <3=> Toggle
// <4=> Force inactive level
// <5=> Force active level
// <6=> PWM mode 1
// <7=> PWM mode 2
// <o11.3> TIM1_CCMR1.OC1PE: Output Compare 1 Preload enabled
// <o11.2> TIM1_CCMR1.OC1FE: Output Compare 1 Fast enabled
// <o11.0..1> TIM1_CCMR1.CC1S: Capture/compare 1 selection
// <i> Default: CC1 configured as output
// <0=> CC1 configured as output
// <o13.3> TIM1_CCER.CC1NP: Capture/compare 1 Complementary output Polarity set
// <i> Default: OC1N active high
// <0=> OC1N active high
// <1=> OC1N active low
// <o13.2> TIM1_CCER.CC1NE: Capture/compare 1 Complementary output enabled
// <i> Default: OC1N not active
// <0=> OC1N not active
// <1=> OC1N is output on corresponding pin
// <o13.1> TIM1_CCER.CC1P: Capture/compare 1 output Polarity set
// <i> Default: OC1 active high
// <0=> OC1 active high
// <1=> OC1 active low
// <o13.0> TIM1_CCER.CC1E: Capture/compare 1 output enabled
// <i> Default: OC1 not active
// <0=> OC1 not active
// <1=> OC1 is output on corresponding pin
// </h>
// <h> Channel configured as input
// <o11.4..7> TIM1_CCMR1.IC1F: Input Capture 1 Filter
// <i> Default: No filter
// <0=> No filter
// <1=> fSampling=fCK_INT, N=2
// <2=> fSampling=fCK_INT, N=4
// <3=> fSampling=fCK_INT, N=8
// <4=> fSampling=fDTS/2, N=6
// <5=> fSampling=fDTS/2, N=8
// <6=> fSampling=fDTS/4, N=6
// <7=> fSampling=fDTS/4, N=8
// <8=> fSampling=fDTS/8, N=6
// <9=> fSampling=fDTS/8, N=8
// <10=> fSampling=fDTS/16, N=5
// <11=> fSampling=fDTS/16, N=6
// <12=> fSampling=fDTS/16, N=8
// <13=> fSampling=fDTS/32, N=5
// <14=> fSampling=fDTS/32, N=6
// <15=> fSampling=fDTS/32, N=8
// <o11.2..3> TIM1_CCMR1.IC1PSC: Input Capture 1 Prescaler
// <i> Default: No prescaler
// <0=> No prescaler
// <1=> capture every 2 events
// <2=> capture every 4 events
// <3=> capture every 8 events
// <o11.0..1> TIM1_CCMR1.CC1S: Capture/compare 1 selection
// <i> Default: CC1 configured as output
// <0=> CC1 configured as output
// <1=> CC1 configured as input, IC1 mapped on TI1
// <2=> CC1 configured as input, IC1 mapped on TI2
// <3=> CC1 configured as input, IC1 mapped on TRGI
// <o13.1> TIM1_CCER.CC1P: Capture/compare 1 output Polarity set
// <i> Default: non-inverted
// <0=> non-inverted
// <1=> inverted
// <o13.0> TIM1_CCER.CC1E: Capture/compare 1 output enabled
// <i> Default: Capture disabled
// <0=> Capture disabled
// <1=> Capture enabled
// </h>
// <o14> TIM1_CCR1: Capture/compare register 1 <0-65535>
// <i> Set the Compare register value for compare register 1.
// <i> Default: 0
// </h>
//
//--------------------------------------------------------------------------- Timer 1 channel 2
// <h> Channel 2 Configuration
// <h> Cannel configured as output
// <o11.15> TIM1_CCMR1.OC2CE: Output Compare 2 Clear enabled
// <o11.12..14> TIM1_CCMR1.OC2M: Output Compare 2 Mode
// <i> Default: Frozen
// <0=> Frozen
// <1=> Set channel 2 to active level on match
// <2=> Set channel 2 to inactive level on match
// <3=> Toggle
// <4=> Force inactive level
// <5=> Force active level
// <6=> PWM mode 1
// <7=> PWM mode 2
// <o11.11> TIM1_CCMR1.OC2PE: Output Compare 2 Preload enabled
// <o11.10> TIM1_CCMR1.OC2FE: Output Compare 2 Fast enabled
// <o11.8..9> TIM1_CCMR1.CC2S: Capture/compare 2 selection
// <i> Default: CC2 configured as output
// <0=> CC2 configured as output
// <o13.7> TIM1_CCER.CC2NP: Capture/compare 2 Complementary output Polarity set
// <i> Default: OC2N active high
// <0=> OC2N active high
// <1=> OC2N active low
// <o13.6> TIM1_CCER.CC2NE: Capture/compare 2 Complementary output enabled
// <i> Default: OC2N not active
// <0=> OC2N not active
// <1=> OC2N is output on corresponding pin
// <o13.5> TIM1_CCER.CC2P: Capture/compare 2 output Polarity set
// <i> Default: OC2 active high
// <0=> OC2 active high
// <1=> OC2 active low
// <o13.4> TIM1_CCER.CC2E: Capture/compare 2 output enabled
// <i> Default: OC2 not active
// <0=> OC2 not active
// <1=> OC2 is output on corresponding pin
// </h>
// <h> Channel configured as input
// <o11.12..15> TIM1_CCMR1.IC2F: Input Capture 2 Filter
// <i> Default: No filter
// <0=> No filter
// <1=> fSampling=fCK_INT, N=2
// <2=> fSampling=fCK_INT, N=4
// <3=> fSampling=fCK_INT, N=8
// <4=> fSampling=fDTS/2, N=6
// <5=> fSampling=fDTS/2, N=8
// <6=> fSampling=fDTS/4, N=6
// <7=> fSampling=fDTS/4, N=8
// <8=> fSampling=fDTS/8, N=6
// <9=> fSampling=fDTS/8, N=8
// <10=> fSampling=fDTS/16, N=5
// <11=> fSampling=fDTS/16, N=6
// <12=> fSampling=fDTS/16, N=8
// <13=> fSampling=fDTS/32, N=5
// <14=> fSampling=fDTS/32, N=6
// <15=> fSampling=fDTS/32, N=8
// <o11.10..11> TIM1_CCMR1.IC2PSC: Input Capture 2 Prescaler
// <i> Default: No prescaler
// <0=> No prescaler
// <1=> capture every 2 events
// <2=> capture every 4 events
// <3=> capture every 8 events
// <o11.8..9> TIM1_CCMR1.CC2S: Capture/compare 2 selection
// <i> Default: CC2 configured as output
// <0=> CC2 configured as output
// <1=> CC2 configured as input, IC2 mapped on TI2
// <2=> CC2 configured as input, IC2 mapped on TI1
// <3=> CC2 configured as input, IC2 mapped on TRGI
// <o13.5> TIM1_CCER.CC2P: Capture/compare 2 output Polarity set
// <i> Default: non-inverted
// <0=> non-inverted
// <1=> inverted
// <o13.4> TIM1_CCER.CC2E: Capture/compare 2 output enabled
// <i> Default: Capture disabled
// <0=> Capture disabled
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