?? stm32_init.c
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// <1=> Capture enabled
// </h>
// <o15> TIM1_CCR2: Capture/compare register 2 <0-65535>
// <i> Set the Compare register value for compare register 2.
// <i> Default: 0
// </h>
//
//--------------------------------------------------------------------------- Timer 1 channel 3
// <h> Channel 3 Configuration
// <h> Cannel configured as output
// <o12.4..6> TIM1_CCMR2.OC3M: Output Compare 3 Mode
// <i> Default: Frozen
// <0=> Frozen
// <1=> Set channel 3 to active level on match
// <2=> Set channel 3 to inactive level on match
// <3=> Toggle
// <4=> Force inactive level
// <5=> Force active level
// <6=> PWM mode 1
// <7=> PWM mode 2
// <o12.3> TIM1_CCMR2.OC3PE: Output Compare 3 Preload enabled
// <o12.2> TIM1_CCMR2.OC3FE: Output Compare 3 Fast enabled
// <o12.0..1> TIM1_CCMR2.CC3S: Capture/compare 3 selection
// <i> Default: CC3 configured as output
// <0=> CC3 configured as output
// <o13.11> TIM1_CCER.CC3NP: Capture/compare 3 Complementary output Polarity set
// <i> Default: OC3N active high
// <0=> OC3N active high
// <1=> OC3N active low
// <o13.10> TIM1_CCER.CC3NE: Capture/compare 3 Complementary output enabled
// <i> Default: OC3N not active
// <0=> OC3N not active
// <1=> OC3N is output on corresponding pin
// <o13.9> TIM1_CCER.CC3P: Capture/compare 3 output Polarity set
// <i> Default: OC3 active high
// <0=> OC3 active high
// <1=> OC3 active low
// <o13.8> TIM1_CCER.CC3E: Capture/compare 3 output enabled
// <i> Default: OC3 not active
// <0=> OC3 not active
// <1=> OC3 is output on corresponding pin
// </h>
// <h> Channel configured as input
// <o12.4..7> TIM1_CCMR2.IC3F: Input Capture 3 Filter
// <i> Default: No filter
// <0=> No filter
// <1=> fSampling=fCK_INT, N=2
// <2=> fSampling=fCK_INT, N=4
// <3=> fSampling=fCK_INT, N=8
// <4=> fSampling=fDTS/2, N=6
// <5=> fSampling=fDTS/2, N=8
// <6=> fSampling=fDTS/4, N=6
// <7=> fSampling=fDTS/4, N=8
// <8=> fSampling=fDTS/8, N=6
// <9=> fSampling=fDTS/8, N=8
// <10=> fSampling=fDTS/16, N=5
// <11=> fSampling=fDTS/16, N=6
// <12=> fSampling=fDTS/16, N=8
// <13=> fSampling=fDTS/32, N=5
// <14=> fSampling=fDTS/32, N=6
// <15=> fSampling=fDTS/32, N=8
// <o12.2..3> TIM1_CCMR2.IC3PSC: Input Capture 3 Prescaler
// <i> Default: No prescaler
// <0=> No prescaler
// <1=> capture every 2 events
// <2=> capture every 4 events
// <3=> capture every 8 events
// <o12.0..1> TIM1_CCMR2.CC3S: Capture/compare 3 selection
// <i> Default: CC3 configured as output
// <0=> CC3 configured as output
// <1=> CC3 configured as input, IC3 mapped on TI3
// <2=> CC3 configured as input, IC3 mapped on TI4
// <3=> CC3 configured as input, IC3 mapped on TRGI
// <o13.9> TIM1_CCER.CC3P: Capture/compare 3 output Polarity set
// <i> Default: non-inverted
// <0=> non-inverted
// <1=> inverted
// <o13.8> TIM1_CCER.CC3E: Capture/compare 3 output enabled
// <i> Default: Capture disabled
// <0=> Capture disabled
// <1=> Capture enabled
// </h>
// <o16> TIM1_CCR3: Capture/compare register 3 <0-65535>
// <i> Set the Compare register value for compare register 3.
// <i> Default: 0
// </h>
//
//--------------------------------------------------------------------------- Timer 1 channel 4
// <h> Channel 4 Configuration
// <h> Cannel configured as output
// <o12.15> TIM1_CCMR2.OC4CE: Output Compare 4 Clear enabled
// <o12.12..14> TIM1_CCMR2.OC4M: Output Compare 4 Mode
// <i> Default: Frozen
// <0=> Frozen
// <1=> Set channel 4 to active level on match
// <2=> Set channel 4 to inactive level on match
// <3=> Toggle
// <4=> Force inactive level
// <5=> Force active level
// <6=> PWM mode 1
// <7=> PWM mode 2
// <o12.11> TIM1_CCMR2.OC4PE: Output Compare 4 Preload enabled
// <o12.10> TIM1_CCMR2.OC4FE: Output Compare 4 Fast enabled
// <o12.8..9> TIM1_CCMR2.CC4S: Capture/compare 4 selection
// <i> Default: CC4 configured as output
// <0=> CC4 configured as output
// <o13.13> TIM1_CCER.CC4P: Capture/compare 4 output Polarity set
// <i> Default: OC4 active high
// <0=> OC4 active high
// <1=> OC4 active low
// <o13.12> TIM1_CCER.CC4E: Capture/compare 4 output enabled
// <i> Default: OC4 not active
// <0=> OC4 not active
// <1=> OC4 is output on corresponding pin
// </h>
// <h> Channel configured as input
// <o12.12..15> TIM1_CCMR2.IC4F: Input Capture 4 Filter
// <i> Default: No filter
// <0=> No filter
// <1=> fSampling=fCK_INT, N=2
// <2=> fSampling=fCK_INT, N=4
// <3=> fSampling=fCK_INT, N=8
// <4=> fSampling=fDTS/2, N=6
// <5=> fSampling=fDTS/2, N=8
// <6=> fSampling=fDTS/4, N=6
// <7=> fSampling=fDTS/4, N=8
// <8=> fSampling=fDTS/8, N=6
// <9=> fSampling=fDTS/8, N=8
// <10=> fSampling=fDTS/16, N=5
// <11=> fSampling=fDTS/16, N=6
// <12=> fSampling=fDTS/16, N=8
// <13=> fSampling=fDTS/32, N=5
// <14=> fSampling=fDTS/32, N=6
// <15=> fSampling=fDTS/32, N=8
// <o12.10..11> TIM1_CCMR2.IC4PSC: Input Capture 4 Prescaler
// <i> Default: No prescaler
// <0=> No prescaler
// <1=> capture every 2 events
// <2=> capture every 4 events
// <3=> capture every 8 events
// <o12.8..9> TIM1_CCMR2.CC4S: Capture/compare 4 selection
// <i> Default: CC4 configured as output
// <0=> CC4 configured as output
// <1=> CC4 configured as input, IC4 mapped on TI4
// <2=> CC4 configured as input, IC4 mapped on TI3
// <3=> CC4 configured as input, IC4 mapped on TRGI
// <o13.13> TIM1_CCER.CC4P: Capture/compare 4 output Polarity set
// <i> Default: non-inverted
// <0=> non-inverted
// <1=> inverted
// <o13.12> TIM1_CCER.CC4E: Capture/compare 4 output enabled
// <i> Default: Capture disabled
// <0=> Capture disabled
// <1=> Capture enabled
// </h>
// <o17> TIM1_CCR4: Capture/compare register 4 <0-65535>
// <i> Set the Compare register value for compare register 4.
// <i> Default: 0
// </h>
//
// <h> Timer1 Break and dead-time register Configuration (TIM1_BDTR)
// <o18.15> TIM1_BDTR.MOE: Main Output enabled
// <o18.14> TIM1_BDTR.AOE: Automatic Output enabled
// <o18.13> TIM1_BDTR.BKP: Break Polarity active high
// <o18.12> TIM1_BDTR.BKE: Break Inputs enabled
// <o18.11> TIM1_BDTR.OSSR: Off-State Selection for Run mode
// <i> Default: OC/OCN output signal=0
// <0=> OC/OCN output signal=0
// <1=> OC/OCN output signal=1
// <o18.10> TIM1_BDTR.OSSI: Off-State Selection for Idle mode
// <i> Default: OC/OCN output signal=0
// <0=> OC/OCN output signal=0
// <1=> OC/OCN output signal=1
// <o18.8..9> TIM1_BDTR.LOCK: Lock Level <0-3>
// <i> Default: 0 (LOCK OFF)
// <o18.0..7> TIM1_BDTR.DTG: Dead-Time Generator set-up <0x00-0xFF>
// </h>
//
// </e>
// <e3.0> TIM1 interrupts
// <o19.14> TIM1_DIER.TDE: Trigger DMA request enabled
// <o19.12> TIM1_DIER.CC4DE: Capture/Compare 4 DMA request enabled
// <o19.11> TIM1_DIER.CC3DE: Capture/Compare 3 DMA request enabled
// <o19.10> TIM1_DIER.CC2DE: Capture/Compare 2 DMA request enabled
// <o19.9> TIM1_DIER.CC1DE: Capture/Compare 1 DMA request enabled
// <o19.8> TIM1_DIER.UDE: Update DMA request enabled
// <o19.7> TIM1_DIER.BIE: Break interrupt enabled
// <o19.6> TIM1_DIER.TIE: Trigger interrupt enabled
// <o19.5> TIM1_DIER.COMIE: COM interrupt enabled
// <o19.4> TIM1_DIER.CC4IE: Capture/Compare 4 interrupt enabled
// <o19.3> TIM1_DIER.CC3IE: Capture/Compare 3 interrupt enabled
// <o19.2> TIM1_DIER.CC2IE: Capture/Compare 2 interrupt enabled
// <o19.1> TIM1_DIER.CC1IE: Capture/Compare 1 interrupt enabled
// <o19.0> TIM1_DIER.UIE: Update interrupt enabled
// </e>
// </e>
//--------------------------------------------------------------------------- Timer 2 enabled
// <e1.1> TIM2 : Timer 2 enabled
// <o20> TIM2 period [us] <1-72000000:10>
// <i> Set the timer period for Timer 2.
// <i> Default: 1000 (1ms)
// <i> Ignored if Detailed settings is selected
// <e2.1> TIM2 detailed settings
//--------------------------------------------------------------------------- Timer 2 detailed settings
// <o21> TIM2.PSC: Timer 2 Prescaler <0-65535>
// <i> Set the prescaler for Timer 2.
// <o22> TIM2.ARR: Timer 2 Auto-reload <0-65535>
// <i> Set the Auto-reload for Timer 2.
// <h> Timer 2 Control Register 1 Configuration (TIM2_CR1)
// <o23.8..9> TIM2_CR1.CKD: Clock division
// <i> Default: tDTS = tCK_INT
// <i> devision ratio between timer clock and dead time
// <0=> tDTS = tCK_INT
// <1=> tDTS = 2*tCK_INT
// <2=> tDTS = 4*tCK_INT
// <o23.7> TIM2_CR1.ARPE: Auto-reload preload enable
// <i> Default: Auto-reload preload disenabled
// <o23.5..6> TIM2_CR1.CMS: Center aligned mode selection
// <i> Default: Edge-aligned
// <0=> Edge-aligned
// <1=> Center-aligned mode1
// <2=> Center-aligned mode2
// <3=> Center-aligned mode3
// <o23.4> TIM2_CR1.DIR: Direction
// <i> Default: DIR = Counter used as up-counter
// <i> read only if timer is configured as Center-aligned or Encoder mode
// <0=> Counter used as up-counter
// <1=> Counter used as down-counter
// <o23.3> TIM2_CR1.OPM: One pulse mode enable
// <i> Default: One pulse mode disabled
// <o23.2> TIM2_CR1.URS: Update request source
// <i> Default: URS = Counter over-/underflow, UG bit, Slave mode controller
// <0=> Counter over-/underflow, UG bit, Slave mode controller
// <1=> Counter over-/underflow
// <o23.1> TIM2_CR1.UDIS: Update disable
// <i> Default: Update enabled
// </h>
//
// <h> Timer 2 Control Register 2 Configuration (TIM2_CR2)
// <o24.7> TIM2_CR2.TI1S: TI1 Selection
// <i> Default: TIM2CH1 connected to TI1 input
// <0=> TIM2CH1 connected to TI1 input
// <1=> TIM2CH1,CH2,CH3 connected to TI1 input
// <o24.4..6> TIM2_CR2.MMS: Master Mode Selection
// <i> Default: Reset
// <i> Select information to be sent in master mode to slave timers for synchronisation
// <0=> Reset
// <1=> Enable
// <2=> Update
// <3=> Compare Pulse
// <4=> Compare OC1REF iused as TRGO
// <5=> Compare OC2REF iused as TRGO
// <6=> Compare OC3REF iused as TRGO
// <7=> Compare OC4REF iused as TRGO
// <o24.3> TIM2_CR2.CCDS: Capture/Compare DMA Selection
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