{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/testlog/DDS_VHDL.fit.smsg " "Info: Generated suppressed messages file C:/testlog/DDS_VHDL.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "182 " "Info: Allocated 182 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 10 19:36:17 2008 " "Info: Processing ended: Sun Aug 10 19:36:17 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 10 19:36:18 2008 " "Info: Processing started: Sun Aug 10 19:36:18 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off DDS_VHDL -c DDS_VHDL " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DDS_VHDL -c DDS_VHDL" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "130 " "Info: Allocated 130 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 10 19:36:22 2008 " "Info: Processing ended: Sun Aug 10 19:36:22 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 10 19:36:23 2008 " "Info: Processing started: Sun Aug 10 19:36:23 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off DDS_VHDL -c DDS_VHDL --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DDS_VHDL -c DDS_VHDL --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "DDS_VHDL.vhd" "" { Text "C:/testlog/DDS_VHDL.vhd" 5 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK memory sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a0~porta_address_reg0 memory sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[0\] 256.02 MHz 3.906 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 256.02 MHz between source memory \"sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a0~porta_address_reg0\" and destination memory \"sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[0\]\" (period= 3.906 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.323 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a0~porta_address_reg0 1 MEM M4K_X17_Y10 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y10; Fanout = 4; MEM Node = 'sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.323 ns) 3.323 ns sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[0\] 2 MEM M4K_X17_Y10 1 " "Info: 2: + IC(0.000 ns) + CELL(3.323 ns) = 3.323 ns; Loc. = M4K_X17_Y10; Fanout = 1; MEM Node = 'sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.323 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.323 ns ( 100.00 % ) " "Info: Total cell delay = 3.323 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.323 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.323 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 3.323ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.011 ns - Smallest " "Info: - Smallest clock skew is -0.011 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.260 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLK\" to destination memory is 2.260 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK PIN_29 102 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 102; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "C:/testlog/DDS_VHDL.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.585 ns) + CELL(0.545 ns) 2.260 ns sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[0\] 2 MEM M4K_X17_Y10 1 " "Info: 2: + IC(0.585 ns) + CELL(0.545 ns) = 2.260 ns; Loc. = M4K_X17_Y10; Fanout = 1; MEM Node = 'sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.130 ns" { CLK sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.675 ns ( 74.12 % ) " "Info: Total cell delay = 1.675 ns ( 74.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.585 ns ( 25.88 % ) " "Info: Total interconnect delay = 0.585 ns ( 25.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/a