?? dds_vhdl.tan.summary
字號:
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Timing Analyzer Summary
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Type : Worst-case tsu
Slack : N/A
Required Time : None
Actual Time : 5.087 ns
From : PWORD[4]
To : REG10B:u5|DOUT[9]
From Clock : --
To Clock : CLK
Failed Paths : 0
Type : Worst-case tco
Slack : N/A
Required Time : None
Actual Time : 6.786 ns
From : sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[3]
To : FOUT[3]
From Clock : CLK
To Clock : --
Failed Paths : 0
Type : Worst-case th
Slack : N/A
Required Time : None
Actual Time : -0.871 ns
From : FWORD[3]
To : REG32B:u2|DOUT[23]
From Clock : --
To Clock : CLK
Failed Paths : 0
Type : Clock Setup: 'CLK'
Slack : N/A
Required Time : None
Actual Time : 256.02 MHz ( period = 3.906 ns )
From : sin_rom:u6|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a8~porta_address_reg9
To : sin_rom:u6|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[9]
From Clock : CLK
To Clock : CLK
Failed Paths : 0
Type : Total number of failed paths
Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0
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