#include <stdio.h>
#include <csl.h>
#include <stdio.h>
#include "c6x.h"
#include "system.h"

#define EMIF_CE2        0x01800010

int flash_page_prog( unsigned int src_addr, unsigned int dst_addr, int page_size);
void flash_chip_erase(void);
void flash_word_prog(unsigned int addr);

unsigned short *ctrladdr1=(unsigned short *)(0x90000000+(0x5555<<1));
unsigned short *ctrladdr2=(unsigned short *)(0x90000000+(0x2aaa<<1));
unsigned int state=0;

#pragma DATA_SECTION(host_buffer, "Host_Buffer")
  unsigned int host_buffer[33];
  unsigned int start_addr, prog_ptr, prog_flag, page_count, checksum, i;
  char *check_ptr;
  unsigned int readdata;
/*-------------------------------------------------------------------------*/
/* main()                                                                  */
/*-------------------------------------------------------------------------*/
void tdelay(unsigned int delay_num)  
   {
    unsigned int i,k;                
    for(i=delay_num;i>0;i--)
     {
      for(k=100;k>0;k--)
       {;}
      }
    }
void CFIQueryExit(void)
{
	*ctrladdr1 = 0xaaaa;
	*ctrladdr2 = 0x5555;
	*ctrladdr1 = 0xf0f0;
	state &= 0xfc;	
}
void SWPIDExit(void)
{
	*ctrladdr1 = 0xf0f0;
	state &= 0xfc;
}   
/*************************/
void ssterase(void)
{
	if(state&1)
	{
		if(state&2)
			SWPIDExit();
		else
			CFIQueryExit();						
	}
   	*ctrladdr1=0xaa;
   	*ctrladdr2=0x55;
   	*ctrladdr1=0x80;
   	*ctrladdr1=0xaa;
   	*ctrladdr2=0x55;
   	*ctrladdr1=0x10;

    while(1)
	{
		unsigned int i;
        i = *((volatile unsigned short *)(0x6666+0x90000000))&0x40;
        tdelay(2000);
		if(i!=*((volatile unsigned short *)(0x6666+0x90000000))&0x40)	//D6 = ~D6
			continue;
		else break;//D6==D6
	}
}
   
void sstwrite(unsigned int romaddr,unsigned short romdata)
{		
		*ctrladdr1= 0xaa;
		
		*ctrladdr2= 0x55;
		
		*ctrladdr1 = 0xa0;
		
		*(unsigned short *)(0x90000000+(romaddr<<1)) = romdata;

}
int main()
{
  unsigned int ii;
  unsigned short ReadData=0;
  unsigned short ReadToFlash=0;
  unsigned short temp;
  FILE  *fptr;
  FILE * fptr2;
  /* dsp and peripheral initialization */    
  CSR=0x100;			           /* disable all interrupts            */
  IER=1;                           /* disable all interrupts except NMI */
  ICR=0xffff;                      /* clear all pending interrupts      */
  ISTP=0x800;
  PLLInit();
  
/*************************************************************************
* Standard 6211/6711 DSK includes 2 MT48LC1M16A1-7 devices = 4MB SDRAM   *
* For these devices use the following parameter:                         *
*   EMIF_SDCTRL=0x07126000                                               *
* If MT48LC1M16A1-10 devices are installed use the following parameter:  *
*   EMIF_SDCTRL=0x07227000                                               *
* /|\ 16Mb parts = 4MB SDRAM /|\   *-------------------------------------*
*----------------------------------*   \|/ 64Mb parts = 16MB SDRAM \|/   *
* If MT48LC4M16A2-10 devices are installed use the following parameter:  *
*   EMIF_SDCTRL=0x57227000                                               *
*************************************************************************/

  *(unsigned volatile int *)EMIF_GCR = 0x3068; /* EMIF global control   */
  *(unsigned volatile int *)EMIF_CE0 = 0x90;   /* EMIF CE0 control 16Bit */
  *(unsigned volatile int *)EMIF_CE1 = 0xffffff13; /* EMIF CE1 control, 16bit async, 
  														so the desired address should 
  														be left-shifted two bit, when 
  														CE1 is setted to be 32Bit*/
  
  *(unsigned volatile int *)EMIF_CE2 = 0xffffff13; /* CE2 - 32-bit asynch on daughterboard */
  
  *(unsigned volatile int *)EMIF_SDCTRL = 0x53116000; /* EMIF SDRAM control   */
  *(unsigned volatile int *)EMIF_SDRP = 0x61a;       /* EMIF SDRM refresh period */
  *(unsigned volatile int *)EMIF_SDEXT= 0x54529;  /* EMIF SDRM extension*/ 
  *(unsigned int *)0x80000800=0x3a99aabb;
  *(unsigned int *)0x807ffff4=0x6d456789;
 /************************************************************/
//  IER=0xc003;                          /* enable interrupts except NMI   */
//  ICR=0xffff;                          /* Clear all pending interrupts        */
//  CSR=0x101;                           /*enable all interrupts*/  
/************************************************************/ 
   for(ii=0;ii<5;ii++){
         
         *(unsigned volatile short *)(0xa0000000 +0x1080) = 0; 
         tdelay(1);
         *(unsigned volatile short *)(0xa0000000 +0x1080)= 0xffff;
         tdelay(1);
    }
    ssterase();
    printf("Now the download program runing...............\n");

	fptr=fopen("F:\\blink.bin", "rb");
    if(fptr==NULL)
      printf("error open file\n");
    ii=0;

    while(!feof(fptr))
       { 
         ReadData=fgetc(fptr);
         ReadToFlash=ReadData;
         ReadData=fgetc(fptr);
         ReadToFlash=(ReadToFlash<<8)+ReadData;  
         sstwrite(ii,ReadToFlash);
;
         ii=ii+1;
         tdelay(3);
         *(unsigned volatile short *)(0xa0000000 +0x1080) = 0; 
         tdelay(3);
         *(unsigned volatile short *)(0xa0000000 +0x1080)= 0xffff; 
        }
    fclose(fptr);
    
    printf("Now checking.... \n");

    fptr = fopen("F:\\blink.bin", "rb");
    if(fptr==NULL)
      printf("error open file to check\n"); 
     ii =0;
     while(!feof(fptr))
       { 
         ReadData=fgetc(fptr);
         ReadToFlash=ReadData;
         ReadData=fgetc(fptr);
         ReadToFlash=(ReadToFlash<<8)+ReadData;  
         ReadToFlash &= 0xffff;

         temp = *(unsigned short *)(0x90000000+(ii<<1));
         temp &= 0xffff;
         if(ReadToFlash != temp){
          printf("error in addr--%x! file is--%x, but flash is--%x\n", 0x90000000+(ii<<1), ReadToFlash, temp);
         }
         ii=ii+1;
        }   
    printf("Download had finished,Please stop the program \n");
    fclose(fptr);
    while(1);
}