?? bahe.map.rpt
字號:
Analysis & Synthesis report for bahe
Tue Mar 03 11:56:44 2009
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. State Machine - |bahe|daojishi:dao|present_state
8. Registers Removed During Synthesis
9. Source assignments for count:cnt|lpm_counter:p1_rtl_0
10. Source assignments for count:cnt|lpm_counter:p2_rtl_1
11. Source assignments for music:mu|table:u1|lpm_counter:counter_rtl_2
12. Parameter Settings for Inferred Entity Instance: count:cnt|lpm_counter:p1_rtl_0
13. Parameter Settings for Inferred Entity Instance: count:cnt|lpm_counter:p2_rtl_1
14. Parameter Settings for Inferred Entity Instance: music:mu|table:u1|lpm_counter:counter_rtl_2
15. Parameter Settings for Inferred Entity Instance: division:div|lpm_add_sub:Add1
16. Parameter Settings for Inferred Entity Instance: music:mu|pulse:u2|lpm_add_sub:Add0
17. Parameter Settings for Inferred Entity Instance: division:div|lpm_add_sub:Add0
18. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Mar 03 11:56:44 2009 ;
; Quartus II Version ; 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name ; bahe ;
; Top-level Entity Name ; bahe ;
; Family ; MAX7000S ;
; Total macrocells ; 122 ;
; Total pins ; 42 ;
+-----------------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------+-----------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------+-----------------+---------------+
; Device ; EPM7128SLC84-15 ; ;
; Top-level entity name ; bahe ; bahe ;
; Family name ; MAX7000S ; Stratix ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A ; Balanced ; Speed ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Auto ; Auto ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Allow XOR Gate Usage ; On ; On ;
; Auto Logic Cell Insertion ; On ; On ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4 ; 4 ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A ; 100 ; 100 ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Use smart compilation ; Off ; Off ;
+----------------------------------------------------------------------+-----------------+---------------+
+---------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------------+----------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+----------------------------------------------------------------------+
; division.vhd ; yes ; User VHDL File ; D:/VHDL+拔河游戲機/bahe/division.vhd ;
; count.vhd ; yes ; User VHDL File ; D:/VHDL+拔河游戲機/bahe/count.vhd ;
; cmp.vhd ; yes ; User VHDL File ; D:/VHDL+拔河游戲機/bahe/cmp.vhd ;
; decode.vhd ; yes ; User VHDL File ; D:/VHDL+拔河游戲機/bahe/decode.vhd ;
; pulse.vhd ; yes ; User VHDL File ; D:/VHDL+拔河游戲機/bahe/pulse.vhd ;
; table.vhd ; yes ; User VHDL File ; D:/VHDL+拔河游戲機/bahe/table.vhd ;
; daojishi.vhd ; yes ; User VHDL File ; D:/VHDL+拔河游戲機/bahe/daojishi.vhd ;
; bahe.vhd ; yes ; User VHDL File ; D:/VHDL+拔河游戲機/bahe/bahe.vhd ;
; music.vhd ; yes ; Other ; D:/VHDL+拔河游戲機/bahe/music.vhd ;
; lpm_counter.tdf ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf ;
; lpm_constant.inc ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/lpm_constant.inc ;
; lpm_decode.inc ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/lpm_decode.inc ;
; lpm_add_sub.inc ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/lpm_add_sub.inc ;
; cmpconst.inc ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/cmpconst.inc ;
; lpm_compare.inc ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/lpm_compare.inc ;
; lpm_counter.inc ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/lpm_counter.inc ;
; dffeea.inc ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/dffeea.inc ;
; alt_synch_counter.inc ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/alt_synch_counter.inc ;
; alt_synch_counter_f.inc ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.inc ;
; alt_counter_stratix.inc ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal71.inc ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/aglobal71.inc ;
; lpm_add_sub.tdf ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/lpm_add_sub.tdf ;
; addcore.inc ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/addcore.inc ;
; look_add.inc ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/look_add.inc ;
; bypassff.inc ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/bypassff.inc ;
; altshift.inc ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/altshift.inc ;
; alt_stratix_add_sub.inc ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ;
; alt_mercury_add_sub.inc ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/alt_mercury_add_sub.inc ;
; addcore.tdf ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/addcore.tdf ;
; a_csnbuffer.inc ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/a_csnbuffer.inc ;
; a_csnbuffer.tdf ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/a_csnbuffer.tdf ;
; altshift.tdf ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/altshift.tdf ;
; look_add.tdf ; yes ; Megafunction ; d:/altera/71/quartus/libraries/megafunctions/look_add.tdf ;
+----------------------------------+-----------------+-----------------+----------------------------------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 122 ;
; Total registers ; 80 ;
; I/O pins ; 42 ;
; Shareable expanders ; 24 ;
; Parallel expanders ; 11 ;
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