; Clock Hold: 'clk_in'         ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; cmp:com|tmp_sta                                     ; cmp:com|tmp_record1[1]                 ; clk_in     ; clk_in   ; 12           ;
; Total number of failed paths ;                                          ;               ;                                  ;                                                     ;                                        ;            ;          ; 12           ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-----------------------------------------------------+----------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM7128SLC84-15    ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; On                 ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk_in          ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; player1         ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; player2         ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk_in'                                                                                                                                                                                                                                                                      ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                ; To                       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 21.28 MHz ( period = 47.000 ns )                    ; music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[0] ; music:mu|pulse:u2|p_1[3] ; clk_in     ; clk_in   ; None                        ; None                      ; 24.000 ns               ;
; N/A                                     ; 21.28 MHz ( period = 47.000 ns )                    ; music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[1] ; music:mu|pulse:u2|p_1[3] ; clk_in     ; clk_in   ; None                        ; None                      ; 24.000 ns               ;
; N/A                                     ; 24.39 MHz ( period = 41.000 ns )                    ; music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[0] ; music:mu|pulse:u2|p_1[5] ; clk_in     ; clk_in   ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 24.39 MHz ( period = 41.000 ns )                    ; music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[1] ; music:mu|pulse:u2|p_1[5] ; clk_in     ; clk_in   ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 24.39 MHz ( period = 41.000 ns )                    ; music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[2] ; music:mu|pulse:u2|p_1[5] ; clk_in     ; clk_in   ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 24.39 MHz ( period = 41.000 ns )                    ; music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[3] ; music:mu|pulse:u2|p_1[5] ; clk_in     ; clk_in   ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 24.39 MHz ( period = 41.000 ns )                    ; music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[4] ; music:mu|pulse:u2|p_1[5] ; clk_in     ; clk_in   ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 25.00 MHz ( period = 40.000 ns )                    ; music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[0] ; music:mu|pulse:u2|p_1[8] ; clk_in     ; clk_in   ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 25.00 MHz ( period = 40.000 ns )                    ; music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[1] ; music:mu|pulse:u2|p_1[8] ; clk_in     ; clk_in   ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 25.00 MHz ( period = 40.000 ns )                    ; music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[2] ; music:mu|pulse:u2|p_1[8] ; clk_in     ; clk_in   ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 25.00 MHz ( period = 40.000 ns )                    ; music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[3] ; music:mu|pulse:u2|p_1[8] ; clk_in     ; clk_in   ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 25.00 MHz ( period = 40.000 ns )                    ; music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[4] ; music:mu|pulse:u2|p_1[8] ; clk_in     ; clk_in   ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 25.00 MHz ( period = 40.000 ns )                    ; music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[0] ; music:mu|pulse:u2|p_1[1] ; clk_in     ; clk_in   ; None                        ; None                      ; 17.000 ns               ;