library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity division is
	port(clk_in:in std_logic;					--1MHz
		 clk_100,clk_5,clk_1:out std_logic);	--100Hz,5Hz,1Hz
end division;

architecture body_division of division is
	--signal count1:integer range 0 to 1;		--仿真用
	signal count1:integer range 0 to 4999;		--100HZ，用于數碼管顯示模塊
	--signal count2:integer range 0 to 1;		--仿真用
	signal count2:integer range 0 to 49;		--100HZ to 1HZ，用于倒記時模塊
	signal count3:integer range 0 to 9;			--100Hz to 5Hz，用于音樂模塊
	signal clk2,clk3,clk4:std_logic;			--分頻后的輸出	

begin
	process(clk_in)								--100Hz
		begin
			if(clk_in'event and clk_in='1') then
				if(count1=4999) then
					count1<=0;
					clk2<=not clk2;
				else count1<=count1+1;
				end if;
			end if;
		end process;
		
	process(clk2)								--5Hz
		begin
			if(clk2'event and clk2='1') then
				if(count2=49) then
					count2<=0;
					clk3<=not clk3;
				else count2<=count2+1;
				end if;
			end if;
		end process;
	
	process(clk2)								--1Hz
		begin
			if(clk2'event and clk2='1') then
				if(count3=9) then
					count3<=0;
					clk4<=not clk4;
				else count3<=count3+1;
				end if;
			end if;
		end process;
	
	clk_100<=clk2;
	clk_1<=clk3;
	clk_5<=clk4;
end body_division;