?? lpc2400.h
字號:
#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A))
#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A))
#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A))
#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C))
#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C))
#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C))
#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C))
#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C))
#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D))
#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3D))
#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D))
#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D))
#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D))
#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E))
#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E))
#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E))
#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E))
#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E))
#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F))
#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F))
#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F))
#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F))
#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F))
#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C))
#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C))
#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C))
#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C))
#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C))
#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E))
#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E))
#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E))
#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E))
#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E))
/*********************************************************************************************************
System Control Block(SCB) modules include Memory Accelerator Module,
Phase Locked Loop, VPB divider, Power Control, External Interrupt,
Reset, and Code Security/Debugging
*********************************************************************************************************/
#define SCB_BASE_ADDR 0xE01FC000
/*********************************************************************************************************
Memory Accelerator Module
*********************************************************************************************************/
#define MAMCR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000))
#define MAMTIM (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004))
#define MEMMAP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x040))
/*********************************************************************************************************
Phase Locked Loop (PLL)
*********************************************************************************************************/
#define PLLCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080))
#define PLLCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084))
#define PLLSTAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088))
#define PLLFEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C))
/*********************************************************************************************************
Power Control
*********************************************************************************************************/
#define PCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0))
#define PCONP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4))
/*********************************************************************************************************
Clock Divider
*********************************************************************************************************/
#define CCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x104))
#define USBCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x108))
#define CLKSRCSEL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C))
#define PCLKSEL0 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8))
#define PCLKSEL1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC))
/*********************************************************************************************************
External Interrupts
*********************************************************************************************************/
#define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140))
#define INTWAKE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144))
#define EXTMODE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148))
#define EXTPOLAR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C))
/*********************************************************************************************************
Reset, reset source identification
*********************************************************************************************************/
#define RSIR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180))
/*********************************************************************************************************
RSID, code security protection
*********************************************************************************************************/
#define CSPR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x184))
#define AHBCFG1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x188))
#define AHBCFG2 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C))
#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0))
#define EMC_BASE_ADDR 0xFFE08000
#define EMCControl (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000))
#define EMCStatus (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004))
#define EMCConfig (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008))
#define EMCDynamicControl (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x020))
#define EMCDynamicRefresh (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x024))
#define EMCDynamicReadConfig (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x028))
#define EMCDynamictRP (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x030))
#define EMCDynamictRAS (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x034))
#define EMCDynamictSREX (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x038))
#define EMCDynamictAPR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x03C))
#define EMCDynamictDAL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x040))
#define EMCDynamictWR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x044))
#define EMCDynamictRC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x048))
#define EMCDynamictRFC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x04C))
#define EMCDynamictXSR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x050))
#define EMCDynamictRRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x054))
#define EMCDynamictMRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x058))
#define EMCDynamicConfig0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x100))
#define EMCDynamicContro1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x120))
#define EMCDynamicContro2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x140))
#define EMCDynamicContro3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x160))
#define EMCDynamicRASCAS0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x104))
#define EMCDynamicRASCAS1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x124))
#define EMCDynamicRASCAS2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x144))
#define EMCDynamicRASCAS3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x164))
#define EMCStaticConfig0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x200))
#define EMCStaticWaitWen0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x204))
#define EMCStaticWaitOen0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x208))
#define EMCStaticWaitRd0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x20C))
#define EMCStaticWaitPage0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x210))
#define EMCStaticWaitWr0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x214))
#define EMCStaticWaitTurn0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x218))
#define EMCStaticConfig1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x220))
#define EMCStaticWaitWen1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x224))
#define EMCStaticWaitOen1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x228))
#define EMCStaticWaitRd1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x22C))
#define EMCStaticWaitPage1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x230))
#define EMCStaticWaitWr1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x234))
#define EMCStaticWaitTurn1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x238))
#define EMCStaticConfig2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x240))
#define EMCStaticWaitWen2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x244))
#define EMCStaticWaitOen2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x248))
#define EMCStaticWaitRd2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x24C))
#define EMCStaticWaitPage2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x250))
#define EMCStaticWaitWr2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x254))
#define EMCStaticWaitTurn2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x258))
#define EMCStaticConfig3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x260))
#define EMCStaticWaitWen3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x264))
#define EMCStaticWaitOen3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x268))
#define EMCStaticWaitRd3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x26C))
#define EMCStaticWaitPage3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x270))
#define EMCStaticWaitWr3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x274))
#define EMCStaticWaitTurn3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x278))
#define EMCStaticExtendedWait (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880))
#define TMR0_BASE_ADDR 0xE0004000
#define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00))
#define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04))
#define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08))
#define T0PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C))
#define T0PC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10))
#define T0MCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14))
#define T0MR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18))
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