?? lpc2400.inc
字號:
;/********************************************************************************************************
; AHB configuration
;********************************************************************************************************/
AHBCFG1 EQU (SCB_BASE_ADDR + 0x188)
AHBCFG2 EQU (SCB_BASE_ADDR + 0x18C)
;/********************************************************************************************************
; System Controls and Status
;********************************************************************************************************/
SCS EQU (SCB_BASE_ADDR + 0x1A0)
;/********************************************************************************************************
; External Memory Controller (EMC)
;********************************************************************************************************/
EMC_BASE_ADDR EQU 0xFFE08000
EMCControl EQU (EMC_BASE_ADDR + 0x000)
EMCStatus EQU (EMC_BASE_ADDR + 0x004)
EMCConfig EQU (EMC_BASE_ADDR + 0x008)
;/********************************************************************************************************
; Static Dynamic RAM access registers
;********************************************************************************************************/
EMCDynamicControl EQU (EMC_BASE_ADDR + 0x020)
EMCDynamicRefresh EQU (EMC_BASE_ADDR + 0x024)
EMCDynamicReadConfig EQU (EMC_BASE_ADDR + 0x028)
EMCDynamictRP EQU (EMC_BASE_ADDR + 0x030)
EMCDynamictRAS EQU (EMC_BASE_ADDR + 0x034)
EMCDynamictSREX EQU (EMC_BASE_ADDR + 0x038)
EMCDynamictAPR EQU (EMC_BASE_ADDR + 0x03C)
EMCDynamictDAL EQU (EMC_BASE_ADDR + 0x040)
EMCDynamictWR EQU (EMC_BASE_ADDR + 0x044)
EMCDynamictRC EQU (EMC_BASE_ADDR + 0x048)
EMCDynamictRFC EQU (EMC_BASE_ADDR + 0x04C)
EMCDynamictXSR EQU (EMC_BASE_ADDR + 0x050)
EMCDynamictRRD EQU (EMC_BASE_ADDR + 0x054)
EMCDynamictMRD EQU (EMC_BASE_ADDR + 0x058)
EMCDynamicConfig0 EQU (EMC_BASE_ADDR + 0x100)
EMCDynamicContro1 EQU (EMC_BASE_ADDR + 0x120)
EMCDynamicContro2 EQU (EMC_BASE_ADDR + 0x140)
EMCDynamicContro3 EQU (EMC_BASE_ADDR + 0x160)
EMCDynamicRASCAS0 EQU (EMC_BASE_ADDR + 0x104)
EMCDynamicRASCAS1 EQU (EMC_BASE_ADDR + 0x124)
EMCDynamicRASCAS2 EQU (EMC_BASE_ADDR + 0x144)
EMCDynamicRASCAS3 EQU (EMC_BASE_ADDR + 0x164)
;/********************************************************************************************************
; Static RAM access registers
;********************************************************************************************************/
EMCStaticConfig0 EQU (EMC_BASE_ADDR + 0x200)
EMCStaticWaitWen0 EQU (EMC_BASE_ADDR + 0x204)
EMCStaticWaitOen0 EQU (EMC_BASE_ADDR + 0x208)
EMCStaticWaitRd0 EQU (EMC_BASE_ADDR + 0x20C)
EMCStaticWaitPage0 EQU (EMC_BASE_ADDR + 0x210)
EMCStaticWaitWr0 EQU (EMC_BASE_ADDR + 0x214)
EMCStaticWaitTurn0 EQU (EMC_BASE_ADDR + 0x218)
EMCStaticConfig1 EQU (EMC_BASE_ADDR + 0x220)
EMCStaticWaitWen1 EQU (EMC_BASE_ADDR + 0x224)
EMCStaticWaitOen1 EQU (EMC_BASE_ADDR + 0x228)
EMCStaticWaitRd1 EQU (EMC_BASE_ADDR + 0x22C)
EMCStaticWaitPage1 EQU (EMC_BASE_ADDR + 0x230)
EMCStaticWaitWr1 EQU (EMC_BASE_ADDR + 0x234)
EMCStaticWaitTurn1 EQU (EMC_BASE_ADDR + 0x238)
EMCStaticConfig2 EQU (EMC_BASE_ADDR + 0x240)
EMCStaticWaitWen2 EQU (EMC_BASE_ADDR + 0x244)
EMCStaticWaitOen2 EQU (EMC_BASE_ADDR + 0x248)
EMCStaticWaitRd2 EQU (EMC_BASE_ADDR + 0x24C)
EMCStaticWaitPage2 EQU (EMC_BASE_ADDR + 0x250)
EMCStaticWaitWr2 EQU (EMC_BASE_ADDR + 0x254)
EMCStaticWaitTurn2 EQU (EMC_BASE_ADDR + 0x258)
EMCStaticConfig3 EQU (EMC_BASE_ADDR + 0x260)
EMCStaticWaitWen3 EQU (EMC_BASE_ADDR + 0x264)
EMCStaticWaitOen3 EQU (EMC_BASE_ADDR + 0x268)
EMCStaticWaitRd3 EQU (EMC_BASE_ADDR + 0x26C)
EMCStaticWaitPage3 EQU (EMC_BASE_ADDR + 0x270)
EMCStaticWaitWr3 EQU (EMC_BASE_ADDR + 0x274)
EMCStaticWaitTurn3 EQU (EMC_BASE_ADDR + 0x278)
EMCStaticExtendedWait EQU (EMC_BASE_ADDR + 0x880)
;/********************************************************************************************************
; Timer 0
;********************************************************************************************************/
TMR0_BASE_ADDR EQU 0xE0004000
T0IR EQU (TMR0_BASE_ADDR + 0x00)
T0TCR EQU (TMR0_BASE_ADDR + 0x04)
T0TC EQU (TMR0_BASE_ADDR + 0x08)
T0PR EQU (TMR0_BASE_ADDR + 0x0C)
T0PC EQU (TMR0_BASE_ADDR + 0x10)
T0MCR EQU (TMR0_BASE_ADDR + 0x14)
T0MR0 EQU (TMR0_BASE_ADDR + 0x18)
T0MR1 EQU (TMR0_BASE_ADDR + 0x1C)
T0MR2 EQU (TMR0_BASE_ADDR + 0x20)
T0MR3 EQU (TMR0_BASE_ADDR + 0x24)
T0CCR EQU (TMR0_BASE_ADDR + 0x28)
T0CR0 EQU (TMR0_BASE_ADDR + 0x2C)
T0CR1 EQU (TMR0_BASE_ADDR + 0x30)
T0CR2 EQU (TMR0_BASE_ADDR + 0x34)
T0CR3 EQU (TMR0_BASE_ADDR + 0x38)
T0EMR EQU (TMR0_BASE_ADDR + 0x3C)
T0CTCR EQU (TMR0_BASE_ADDR + 0x70)
;/********************************************************************************************************
; Timer 1
;********************************************************************************************************/
TMR1_BASE_ADDR EQU 0xE0008000
T1IR EQU (TMR1_BASE_ADDR + 0x00)
T1TCR EQU (TMR1_BASE_ADDR + 0x04)
T1TC EQU (TMR1_BASE_ADDR + 0x08)
T1PR EQU (TMR1_BASE_ADDR + 0x0C)
T1PC EQU (TMR1_BASE_ADDR + 0x10)
T1MCR EQU (TMR1_BASE_ADDR + 0x14)
T1MR0 EQU (TMR1_BASE_ADDR + 0x18)
T1MR1 EQU (TMR1_BASE_ADDR + 0x1C)
T1MR2 EQU (TMR1_BASE_ADDR + 0x20)
T1MR3 EQU (TMR1_BASE_ADDR + 0x24)
T1CCR EQU (TMR1_BASE_ADDR + 0x28)
T1CR0 EQU (TMR1_BASE_ADDR + 0x2C)
T1CR1 EQU (TMR1_BASE_ADDR + 0x30)
T1CR2 EQU (TMR1_BASE_ADDR + 0x34)
T1CR3 EQU (TMR1_BASE_ADDR + 0x38)
T1EMR EQU (TMR1_BASE_ADDR + 0x3C)
T1CTCR EQU (TMR1_BASE_ADDR + 0x70)
;/********************************************************************************************************
; Timer 2
;********************************************************************************************************/
TMR2_BASE_ADDR EQU 0xE0070000
T2IR EQU (TMR2_BASE_ADDR + 0x00)
T2TCR EQU (TMR2_BASE_ADDR + 0x04)
T2TC EQU (TMR2_BASE_ADDR + 0x08)
T2PR EQU (TMR2_BASE_ADDR + 0x0C)
T2PC EQU (TMR2_BASE_ADDR + 0x10)
T2MCR EQU (TMR2_BASE_ADDR + 0x14)
T2MR0 EQU (TMR2_BASE_ADDR + 0x18)
T2MR1 EQU (TMR2_BASE_ADDR + 0x1C)
T2MR2 EQU (TMR2_BASE_ADDR + 0x20)
T2MR3 EQU (TMR2_BASE_ADDR + 0x24)
T2CCR EQU (TMR2_BASE_ADDR + 0x28)
T2CR0 EQU (TMR2_BASE_ADDR + 0x2C)
T2CR1 EQU (TMR2_BASE_ADDR + 0x30)
T2CR2 EQU (TMR2_BASE_ADDR + 0x34)
T2CR3 EQU (TMR2_BASE_ADDR + 0x38)
T2EMR EQU (TMR2_BASE_ADDR + 0x3C)
T2CTCR EQU (TMR2_BASE_ADDR + 0x70)
;/********************************************************************************************************
; Timer 3
;********************************************************************************************************/
TMR3_BASE_ADDR EQU 0xE0074000
T3IR EQU (TMR3_BASE_ADDR + 0x00)
T3TCR EQU (TMR3_BASE_ADDR + 0x04)
T3TC EQU (TMR3_BASE_ADDR + 0x08)
T3PR EQU (TMR3_BASE_ADDR + 0x0C)
T3PC EQU (TMR3_BASE_ADDR + 0x10)
T3MCR EQU (TMR3_BASE_ADDR + 0x14)
T3MR0 EQU (TMR3_BASE_ADDR + 0x18)
T3MR1 EQU (TMR3_BASE_ADDR + 0x1C)
T3MR2 EQU (TMR3_BASE_ADDR + 0x20)
T3MR3 EQU (TMR3_BASE_ADDR + 0x24)
T3CCR EQU (TMR3_BASE_ADDR + 0x28)
T3CR0 EQU (TMR3_BASE_ADDR + 0x2C)
T3CR1 EQU (TMR3_BASE_ADDR + 0x30)
T3CR2 EQU (TMR3_BASE_ADDR + 0x34)
T3CR3 EQU (TMR3_BASE_ADDR + 0x38)
T3EMR EQU (TMR3_BASE_ADDR + 0x3C)
T3CTCR EQU (TMR3_BASE_ADDR + 0x70)
;/********************************************************************************************************
; Pulse Width Modulator (PWM)
;********************************************************************************************************/
PWM0_BASE_ADDR EQU 0xE0014000
PWM0IR EQU (PWM0_BASE_ADDR + 0x00)
PWM0TCR EQU (PWM0_BASE_ADDR + 0x04)
PWM0TC EQU (PWM0_BASE_ADDR + 0x08)
PWM0PR EQU (PWM0_BASE_ADDR + 0x0C)
PWM0PC EQU (PWM0_BASE_ADDR + 0x10)
PWM0MCR EQU (PWM0_BASE_ADDR + 0x14)
PWM0MR0 EQU (PWM0_BASE_ADDR + 0x18)
PWM0MR1 EQU (PWM0_BASE_ADDR + 0x1C)
PWM0MR2 EQU (PWM0_BASE_ADDR + 0x20)
PWM0MR3 EQU (PWM0_BASE_ADDR + 0x24)
PWM0CCR EQU (PWM0_BASE_ADDR + 0x28)
PWM0CR0 EQU (PWM0_BASE_ADDR + 0x2C)
PWM0CR1 EQU (PWM0_BASE_ADDR + 0x30)
PWM0CR2 EQU (PWM0_BASE_ADDR + 0x34)
PWM0CR3 EQU (PWM0_BASE_ADDR + 0x38)
PWM0EMR EQU (PWM0_BASE_ADDR + 0x3C)
PWM0MR4 EQU (PWM0_BASE_ADDR + 0x40)
PWM0MR5 EQU (PWM0_BASE_ADDR + 0x44)
PWM0MR6 EQU (PWM0_BASE_ADDR + 0x48)
PWM0PCR EQU (PWM0_BASE_ADDR + 0x4C)
PWM0LER EQU (PWM0_BASE_ADDR + 0x50)
PWM0CTCR EQU (PWM0_BASE_ADDR + 0x70)
PWM1_BASE_ADDR EQU 0xE0018000
PWM1IR EQU (PWM1_BASE_ADDR + 0x00)
PWM1TCR EQU (PWM1_BASE_ADDR + 0x04)
PWM1TC EQU (PWM1_BASE_ADDR + 0x08)
PWM1PR EQU (PWM1_BASE_ADDR + 0x0C)
PWM1PC EQU (PWM1_BASE_ADDR + 0x10)
PWM1MCR EQU (PWM1_BASE_ADDR + 0x14)
PWM1MR0 EQU (PWM1_BASE_ADDR + 0x18)
PWM1MR1 EQU (PWM1_BASE_ADDR + 0x1C)
PWM1MR2 EQU (PWM1_BASE_ADDR + 0x20)
PWM1MR3 EQU (PWM1_BASE_ADDR + 0x24)
PWM1CCR EQU (PWM1_BASE_ADDR + 0x28)
PWM1CR0 EQU (PWM1_BASE_ADDR + 0x2C)
PWM1CR1 EQU (PWM1_BASE_ADDR + 0x30)
PWM1CR2 EQU (PWM1_BASE_ADDR + 0x34)
PWM1CR3 EQU (PWM1_BASE_ADDR + 0x38)
PWM1EMR EQU (PWM1_BASE_ADDR + 0x3C)
PWM1MR4 EQU (PWM1_BASE_ADDR + 0x40)
PWM1MR5 EQU (PWM1_BASE_ADDR + 0x44)
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