mtdcr (memcfga, mem_rtr);		tmp = mfdcr (memcfgd) & ~0x3FF80000;		tmp |= 0x07F00000;	} else {		/* get SDRAM refresh interval register */		mtdcr (memcfga, mem_rtr);		tmp = mfdcr (memcfgd) & ~0x3FF80000;		tmp |= 0x05F00000;	}	/* write SDRAM refresh interval register */	mtdcr (memcfga, mem_rtr);	mtdcr (memcfgd, tmp);	/* enable ECC if used */#if 1	if (sdram_table[i].ecc) {		/* disable checking for all banks */#ifdef SDRAM_DEBUG		serial_puts ("disable ECC.. ");#endif		mtdcr (memcfga, mem_ecccf);		tmp = mfdcr (memcfgd);		tmp &= 0xff0fffff;		/* disable all banks */		mtdcr (memcfga, mem_ecccf);		/* set up SDRAM Controller with ECC enabled */#ifdef SDRAM_DEBUG		serial_puts ("setup SDRAM Controller.. ");#endif		mtdcr (memcfgd, tmp);		mtdcr (memcfga, mem_mcopt1);		tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000;		mtdcr (memcfga, mem_mcopt1);		mtdcr (memcfgd, tmp);		udelay (600);#ifdef SDRAM_DEBUG		serial_puts ("fill the memory..\n");#endif		serial_puts (".");		/* now, fill all the memory */		tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz);		p = (unsigned long) 0;		while ((unsigned long) p < tmp) {			*p++ = 0L;			if (!((unsigned long) p % 0x00800000))	/* every 8MByte */				serial_puts (".");		}		/* enable bank 0 */		serial_puts (".");#ifdef SDRAM_DEBUG		serial_puts ("enable ECC\n");#endif		udelay (400);		mtdcr (memcfga, mem_ecccf);		tmp = mfdcr (memcfgd);		tmp |= 0x00800000;		/* enable bank 0 */		mtdcr (memcfgd, tmp);		udelay (400);	} else#endif	{		/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */		mtdcr (memcfga, mem_mcopt1);		tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80C00000;		mtdcr (memcfga, mem_mcopt1);		mtdcr (memcfgd, tmp);		udelay (400);	}	serial_puts ("\n");	return (0);}int board_pre_init (void){	init_sdram ();   /*-------------------------------------------------------------------------+   | Interrupt controller setup for the PIP405 board.   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive   |       IRQ 16    405GP internally generated; active low; level sensitive   |       IRQ 17-24 RESERVED   |       IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive   |       IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive   |       IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive   | Note for MIP405 board:   |       An interrupt taken for the SouthBridge (IRQ 25) indicates that   |       the Interrupt Controller in the South Bridge has caused the   |       interrupt. The IC must be read to determine which device   |       caused the interrupt.   |   +-------------------------------------------------------------------------*/	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */	mtdcr (uicer, 0x00000000);	/* disable all ints */	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical (for now) */	mtdcr (uicpr, 0xFFFFFF80);	/* set int polarities */	mtdcr (uictr, 0x10000000);	/* set int trigger levels */	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */	return 0;}/* * Get some PLD Registers */unsigned short get_pld_parvers (void){	unsigned short result;	unsigned char rc;	rc = in8 (PLD_PART_REG);	result = (unsigned short) rc << 8;	rc = in8 (PLD_VERS_REG);	result |= rc;	return result;}void user_led0 (unsigned char on){	if (on)		out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4));	else		out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb));}void ide_set_reset (int idereset){	/* if reset = 1 IDE reset will be asserted */	if (idereset)		out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1));	else {		udelay (10000);		out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe));	}}/* ------------------------------------------------------------------------- *//* * Check Board Identity: */int checkboard (void){	unsigned char s[50];	unsigned char bc, var, rc;	int i;	backup_t *b = (backup_t *) s;	puts ("Board: ");	bc = get_board_revcfg ();	var = ~bc;	var &= 0xf;	rc = 0;	for (i = 0; i < 4; i++) {		rc <<= 1;		rc += (var & 0x1);		var >>= 1;	}	rc++;	i = getenv_r ("serial#", s, 32);	if ((i == 0) || strncmp (s, "MIP405", 6)) {		get_backup_values (b);		if (strncmp (b->signature, "MPL\0", 4) != 0) {			puts ("### No HW ID - assuming MIP405");			printf ("-%d Rev %c", rc, 'A' + ((bc >> 4) & 0xf));		} else {			b->serial_name[6] = 0;			printf ("%s-%d Rev %c SN: %s", b->serial_name, rc,					'A' + ((bc >> 4) & 0xf), &b->serial_name[7]);		}	} else {		s[6] = 0;		printf ("%s-%d Rev %c SN: %s", s, rc, 'A' + ((bc >> 4) & 0xf),				&s[7]);	}	bc = in8 (PLD_EXT_CONF_REG);	printf (" Boot Config: 0x%x\n", bc);	return (0);}/* ------------------------------------------------------------------------- *//* ------------------------------------------------------------------------- *//*  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of  the necessary info for SDRAM controller configuration*//* ------------------------------------------------------------------------- *//* ------------------------------------------------------------------------- */static int test_dram (unsigned long ramsize);long int initdram (int board_type){	unsigned long bank_reg[4], tmp, bank_size;	int i, ds;	unsigned long TotalSize;	ds = 0;	/* since the DRAM controller is allready set up, calculate the size with the	   bank registers    */	mtdcr (memcfga, mem_mb0cf);	bank_reg[0] = mfdcr (memcfgd);	mtdcr (memcfga, mem_mb1cf);	bank_reg[1] = mfdcr (memcfgd);	mtdcr (memcfga, mem_mb2cf);	bank_reg[2] = mfdcr (memcfgd);	mtdcr (memcfga, mem_mb3cf);	bank_reg[3] = mfdcr (memcfgd);	TotalSize = 0;	for (i = 0; i < 4; i++) {		if ((bank_reg[i] & 0x1) == 0x1) {			tmp = (bank_reg[i] >> 17) & 0x7;			bank_size = 4 << tmp;			TotalSize += bank_size;		} else			ds = 1;	}	mtdcr (memcfga, mem_ecccf);	tmp = mfdcr (memcfgd);	if (!tmp)		printf ("No ");	printf ("ECC ");	test_dram (TotalSize * MEGA_BYTE);	return (TotalSize * MEGA_BYTE);}/* ------------------------------------------------------------------------- */extern int mem_test (unsigned long start, unsigned long ramsize,					 int quiet);static int test_dram (unsigned long ramsize){#ifdef SDRAM_DEBUG	mem_test (0L, ramsize, 1);#endif	/* not yet implemented */	return (1);}int misc_init_r (void){	return (0);}void print_mip405_rev (void){	unsigned char part, vers, cfg, rev;	cfg = get_board_revcfg ();	vers = cfg;	vers &= 0xf;	rev = (((vers & 0x1) ? 0x8 : 0) |		   ((vers & 0x2) ? 0x4 : 0) |		   ((vers & 0x4) ? 0x2 : 0) | ((vers & 0x8) ? 0x1 : 0));	part = in8 (PLD_PART_REG);	vers = in8 (PLD_VERS_REG);	printf ("Rev:   MIP405-%d Rev %c PLD%d Vers %d\n",			(16 - rev), ((cfg >> 4) & 0xf) + 'A', part, vers);}int last_stage_init (void){	if (miiphy_write (0x1, 0x14, 0x2402) != 0) {		printf ("Error writing to the PHY\n");	}	print_mip405_rev ();	show_stdio_dev ();	check_env ();	return 0;}/*************************************************************************** * some helping routines */int overwrite_console (void){	return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0);	/* return TRUE if console should be overwritten */}/************************************************************************* Print MIP405 Info************************************************************************/void print_mip405_info (void){	unsigned char part, vers, cfg, irq_reg, com_mode, ext;	part = in8 (PLD_PART_REG);	vers = in8 (PLD_VERS_REG);	cfg = in8 (PLD_BOARD_CFG_REG);	irq_reg = in8 (PLD_IRQ_REG);	com_mode = in8 (PLD_COM_MODE_REG);	ext = in8 (PLD_EXT_CONF_REG);	printf ("PLD Part %d version %d\n", part, vers);	printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A');	printf ("Population Options %d %d %d %d\n", (cfg) & 0x1,			(cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);	printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");	printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);	printf ("Test ist %x\n", com_mode);	printf ("User Config Switch %d %d %d %d %d %d %d %d\n",			(ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,			(ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,			(ext >> 6) & 0x1, (ext >> 7) & 0x1);	printf ("SER1 uses handshakes %s\n",			(ext & 0x80) ? "DTR/DSR" : "RTS/CTS");	printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");	printf ("IRQs:\n");	printf ("  PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");	printf ("  UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");	printf ("  UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");	printf ("  PIIX SMI:  %s\n", (irq_reg & 0x10) ? "inactive" : "active");	printf ("  PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active");	printf ("  PIIX NMI:  %s\n", (irq_reg & 0x4) ? "inactive" : "active");}