#$Id: //depot/sw/branches/ART_V53_dragon/bringup/ar5k/config/ar5005g_cb53g.eep#1 $

#EEPROM file for AR5005X 802.11 b/g Cardbus Reference Design card

@cal_section_begin          		# begin @cal section

TARGET_POWER_FILENAME      =  calTrgtPwr_ar5005g_cb53g.txt ; # target power file for calibration
SUBSYSTEM_ID	           =  0x1054;   # Subsystem ID in hex
EEPROM_MAP_TYPE		   =  2;	# Flag indicating eeprom layout type
TURBO_DISABLE	    	   =  0;   	# Prevents software from using TURBO modes
RF_SILENT		   =  0;   	# Cards enabled with RFSilent can be easily silenced
DEVICE_TYPE		   =  1;   	# 1=>Cardbus, 2=>PCI, 3=>miniPCI, 4=>AP
TURBO_MAXPOWER_5G	   =  19.0;   	# Recommended max power in turbo mode to consume less than 2W.
TURBO_MAXPOWER_2p5G	   =  19.0;   	# Recommended max power in turbo mode at 2.5 GHz to consume less than 2W.
A_MODE		           =  0;   	# Whether the adapter supports 802.11a functionality
B_MODE		           =  1;   	# Whether the adapter supports 802.11b functionality
G_MODE		           =  1;   	# Whether the adapter supports 802.11g functionality
ANTENNA_GAIN_5G	           =  0;	# Antenna gain at 5.5GHz. 8-bit signed val in 0.5dB steps.
ANTENNA_GAIN_2p5G          =  1.5;	# Antenna gain at 2.5GHz. 8-bit signed val in 0.5dB steps.
XLNA_GAIN		   =   0;  	# xLNA gain in dB (per AS 6/14/02)
NOISE_FLOOR_THRESHOLD	   = -54; 	# noise floor threshold value (per JHfmn 6/14/02)
11b_XLNA_GAIN		   =  12;  	# xLNA gain in dB
11b_NOISE_FLOOR_THRESHOLD  = -1; 	# noise floor threshold value
11g_XLNA_GAIN		   =  12;  	# xLNA gain in dB
11g_NOISE_FLOOR_THRESHOLD  = -1; 	# noise floor threshold value
11a_FALSE_DETECT_BACKOFF   =  0;	# in dB. only affects channels w/ clock harmonic overlap.
11b_FALSE_DETECT_BACKOFF   =  0;	# in dB. only affects channels w/ clock harmonic overlap.
11g_FALSE_DETECT_BACKOFF   =  0;	# in dB. only affects channels w/ clock harmonic overlap.
11g_TURBO_DISABLE          =  1;        # Set to 1 to disable TURBO mode in 11g
CCK_OFDM_DELTA		   =  -0.5;	# in dB with 0.1dB resolution. In 11g, delta in output power for 1mbps and 6mbps
					# for any given pcdac.
CH14_FILTER_CCK_DELTA	   =  0.5;	# in dB with 0.1dB resolution. In 11g & 11b, delta in output power for ch14 and ch1 - ch13
					# for any given pcdac. This delta arises due to special filter requirement for ch14 (2484).
ENABLE_32KHZ               =  0;	# Flag indicating the presence of the 32kHz sleep crystal

#new capabilities bits
UART_ENABLE                =  0;	# Set to 1 if board supports a UART
COMPRESSION_DISABLE        =  1;        # Set to 1 if compression is not supported
AES_DISABLE                =  0;        # Set to 1 if AES is not supported
FAST_FRAME_DISABLE         =  1;        # Set to 1 if fast frames are not supported
BURSTING_DISABLE           =  0;        # Set to 1 if bursting is not supported
MAX_NUM_QCU                =  0;        # Max QCU's supported [31-0] [0 = will not modify current limit of 10]
KEY_CACHE_SIZE             =  0;	# Key Cache size as 2^[15-1] [0 = will not modify current limit of 128]
EEPROM_SIZE                = 32;    # size in kbits of the eeprom
XR_DISABLE                 =  0;        # set to disable XR

@cal_section_end            		# end @cal section	


@config_section_begin       		# begin @config section

#Antenna Switch Table
#6 bit (msb:lsb) value are mapped to [atten5, atten2, antD, antC, antB, antA]
#----------------------------------------------------------------------------------
@MODE: MODE_SPECIFIC             11a   11a_turbo        11b         11g    11g_tubo
#----------------------------------------------------------------------------------
bb_switch_table_r1x12           0x00        0x00        0x21       0x21      0x21 #(AntCtl 5)
bb_switch_table_r1x2            0x00        0x00        0x21       0x21      0x21 #(AntCtl 4)
bb_switch_table_r1x1            0x00        0x00        0x25       0x25      0x25 #(AntCtl 3)
bb_switch_table_r1              0x00        0x00        0x25       0x25      0x25 #(AntCtl 2)
bb_switch_table_t1              0x00        0x00        0x02       0x02      0x02 #(AntCtl 1)

bb_switch_table_r2x12           0x00        0x00        0x22       0x22      0x22 #(AntCtl 10)
bb_switch_table_r2x2            0x00        0x00        0x22       0x22      0x22 #(AntCtl 9)
bb_switch_table_r2x1            0x00        0x00        0x26       0x26      0x26 #(AntCtl 8)
bb_switch_table_r2              0x00        0x00        0x26       0x26      0x26 #(AntCtl 7)
bb_switch_table_t2              0x00        0x00        0x01       0x01      0x01 #(AntCtl 6)

bb_rxtx_margin_2ghz                0          00          25         25	       25
bb_switch_settling                 0           0          35         49        98
bb_txrxatten                       0           0          28         28        28
bb_pga_desired_size                0           0         -80        -80       -80
bb_adc_desired_size                0           0         -38        -38       -32
rf_ob                              0           0           3          3         3
rf_db                              0           0           5          5         5

bb_thresh62		           0	       0	  28	     28        28
bb_tx_end_to_xpab_off              0           0           0          0         0
bb_tx_frame_to_xpab_on		   0           0         0x7        0xe       0xe


@config_section_end         # end @config section