?? ar5005g_cb63g.eep
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#EEPROM file for AR5513 CB63
@cal_section_begin # begin @cal section
TARGET_POWER_FILENAME = calTrgtPwr_ar5005g_cb63.txt; # target power file for calibration
SUBSYSTEM_ID = 0x2057; # Subsystem ID in hex
EEPROM_MAP_TYPE = 1; # Flag indicating eeprom layout type
TURBO_DISABLE = 0; # Prevents software from using TURBO modes
RF_SILENT = 0; # Cards enabled with RFSilent can be easily silenced
DEVICE_TYPE = 1; # 1=>Cardbus, 2=>PCI, 3=>miniPCI, 4=>AP
TURBO_MAXPOWER_5G = 16.0; # Recommended max power in turbo mode to consume less than 2W.
TURBO_MAXPOWER_2p5G = 16.0; # Recommended max power in turbo mode at 2.5 GHz to consume less than 2W.
A_MODE = 0; # Whether the adapter supports 802.11a functionality
B_MODE = 1; # Whether the adapter supports 802.11b functionality
G_MODE = 1; # Whether the adapter supports 802.11g functionality
ANTENNA_GAIN_5G = 2; # Antenna gain at 5GHz. 8-bit signed val in 0.5dB steps.
ANTENNA_GAIN_2p5G = 2; # Antenna gain at 2.5GHz. 8-bit signed val in 0.5dB steps.
XLNA_GAIN = 13; # xLNA gain in dB (per AS 6/14/02)
NOISE_FLOOR_THRESHOLD = -54; # noise floor threshold value (per JHfmn 6/14/02)
11b_XLNA_GAIN = 13; # xLNA gain in dB
11b_NOISE_FLOOR_THRESHOLD = -1; # noise floor threshold value
11g_XLNA_GAIN = 13; # xLNA gain in dB
11g_NOISE_FLOOR_THRESHOLD = -1; # noise floor threshold value
11a_FALSE_DETECT_BACKOFF = 0; # in dB. only affects channels w/ clock harmonic overlap.
11b_FALSE_DETECT_BACKOFF = 0; # in dB. only affects channels w/ clock harmonic overlap.
11g_FALSE_DETECT_BACKOFF = 0; # in dB. only affects channels w/ clock harmonic overlap.
11g_TURBO_DISABLE = 0; # Set to 1 to disable TURBO mode in 11g
CCK_OFDM_DELTA = 1; # in dB with 0.1dB resolution. In 11g, delta in output power for 1mbps and 6mbps
# for any given pcdac.
CH14_FILTER_CCK_DELTA = 1.5; # in dB with 0.1dB resolution. In 11g & 11b, delta in output power for ch14 and ch1 - ch13
# for any given pcdac. This delta arises due to special filter requirement for ch14 (2484).
ENABLE_32KHZ = 0; # Flag indicating the presence of the 32kHz sleep crystal
TX_CHAIN_MASK = 1; # mask indicating which chains are populated for TX (0x1-->chain0, 0x2-->chain1)
RX_CHAIN_MASK = 3; # mask indicating which chains are populated for RX (0x1-->chain0, 0x2-->chain1)
MBAR_MASK = 3; # mask to hide mbars : 0-->none, 1-->hide mbar1,
# 2-->hide mbar2, 3-->hide mbar1 and mbar2
PCI_CONFIG_BASE_OFFSET = 0x00 # base offset for pci configuration
USE_EEPROM = 1; # whether the design has a flash (0) or eeprom (1)
@cal_section_end # end @cal section
@config_section_begin # begin @config section
#Antenna Switch Table
#6 bit (msb:lsb) value are mapped to [atten5, atten2, antD, antC, antB, antA]
#-----------------------------------------------------------------------------------
@MODE: MODE_SPECIFIC 11a 11a_turbo 11b 11g 11g_turbo
#-----------------------------------------------------------------------------------
bb_switch_table_r1x12 0x00 0x00 0x01 0x01 0x01 #(AntCtl 5)
bb_switch_table_r1x2 0x00 0x00 0x01 0x01 0x01 #(AntCtl 4)
bb_switch_table_r1x1 0x00 0x00 0x01 0x01 0x01 #(AntCtl 3)
bb_switch_table_r1 0x05 0x05 0x09 0x09 0x09 #(AntCtl 2)
bb_switch_table_t1 0x02 0x02 0x02 0x02 0x02 #(AntCtl 1)
bb_switch_table_r2x12 0x00 0x00 0x02 0x02 0x02 #(AntCtl 10)
bb_switch_table_r2x2 0x00 0x00 0x02 0x02 0x02 #(AntCtl 9)
bb_switch_table_r2x1 0x00 0x00 0x02 0x02 0x02 #(AntCtl 8)
bb_switch_table_r2 0x06 0x06 0x0A 0x0A 0x0A #(AntCtl 7)
bb_switch_table_t2 0x01 0x01 0x01 0x01 0x01 #(AntCtl 6)
chn1_bb_switch_table_r1x12 0x00 0x00 0x01 0x01 0x01 #(AntCtl 5)
chn1_bb_switch_table_r1x2 0x00 0x00 0x01 0x01 0x01 #(AntCtl 4)
chn1_bb_switch_table_r1x1 0x00 0x00 0x01 0x01 0x01 #(AntCtl 3)
chn1_bb_switch_table_r1 0x05 0x05 0x09 0x09 0x09 #(AntCtl 2)
chn1_bb_switch_table_t1 0x02 0x02 0x02 0x02 0x02 #(AntCtl 1)
chn1_bb_switch_table_r2x12 0x00 0x00 0x02 0x02 0x02 #(AntCtl 10)
chn1_bb_switch_table_r2x2 0x00 0x00 0x02 0x02 0x02 #(AntCtl 9)
chn1_bb_switch_table_r2x1 0x00 0x00 0x02 0x02 0x02 #(AntCtl 8)
chn1_bb_switch_table_r2 0x06 0x06 0x0A 0x0A 0x0A #(AntCtl 7)
chn1_bb_switch_table_t2 0x01 0x01 0x01 0x01 0x01 #(AntCtl 6)
bb_rxtx_margin_2ghz 0 0 23 20 20
bb_switch_settling 0x2d 0x5a 0x23 0x46 0x6a
bb_txrxatten 15 15 38 25 25
bb_pga_desired_size -80 -80 -80 -80 -80
bb_adc_desired_size -32 -32 -38 -32 -32
rf_ob 2 2 2 2 2
rf_db 2 2 2 2 2
rf_b_ob 2 2 2 2 2
rf_b_db 2 2 2 2 2
rf_xpdsel 1 1 1 1 1
rf_pdgain_lo 0x0 0x0 0x0 0x0 0x0
rf_pdgain_hi 0x0 0x0 0x0 0x0 0x0
#rf_pdgain_hi 0x3 0x3 0x3 0x3 0x3
bb_thresh62 15 15 28 28 28
bb_tx_end_to_xpab_off 0 0 0 0 0
bb_tx_end_to_xpaa_off 0 0 0 0 0
bb_tx_frame_to_xpab_on 0x0e 0xe 0x7 0xe 0xe
bb_tx_frame_to_xpaa_on 0x0e 0xe 0x7 0xe 0xe
bb_tx_end_to_xlna_on 2 2 2 2 2
rf_gain_I 0x0a 0x0a 0x0a 0x0a 0x0a
@config_section_end # end @config section
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