/* system.h * * Machine generated for a CPU named "cpu" as defined in: * d:\GX_CIDE_SOPC\EP2C20_dep\cide_7f\software\syslib\..\..\nios2_7f.ptf * * Generated: 2008-12-03 10:46:46.781 * */#ifndef __SYSTEM_H_#define __SYSTEM_H_/*DO NOT MODIFY THIS FILE   Changing this file will have subtle consequences   which will almost certainly lead to a nonfunctioning   system. If you do modify this file, be aware that your   changes will be overwritten and lost when this file   is generated again.DO NOT MODIFY THIS FILE*//*******************************************************************************                                                                             ** License Agreement                                                           **                                                                             ** Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           ** All rights reserved.                                                        **                                                                             ** Permission is hereby granted, free of charge, to any person obtaining a     ** copy of this software and associated documentation files (the "Software"),  ** to deal in the Software without restriction, including without limitation   ** the rights to use, copy, modify, merge, publish, distribute, sublicense,    ** and/or sell copies of the Software, and to permit persons to whom the       ** Software is furnished to do so, subject to the following conditions:        **                                                                             ** The above copyright notice and this permission notice shall be included in  ** all copies or substantial portions of the Software.                         **                                                                             ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  ** IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    ** FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ** AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      ** LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     ** FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         ** DEALINGS IN THE SOFTWARE.                                                   **                                                                             ** This agreement shall be governed in all respects by the laws of the State   ** of California and by the laws of the United States of America.              **                                                                             *******************************************************************************//* * system configuration * */#define ALT_SYSTEM_NAME "nios2_7f"#define ALT_CPU_NAME "cpu"#define ALT_CPU_ARCHITECTURE "altera_nios2"#define ALT_DEVICE_FAMILY "CYCLONEII"#define ALT_STDIN "/dev/jtag_uart"#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"#define ALT_STDIN_BASE 0x00502890#define ALT_STDIN_DEV jtag_uart#define ALT_STDIN_PRESENT#define ALT_STDOUT "/dev/jtag_uart"#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"#define ALT_STDOUT_BASE 0x00502890#define ALT_STDOUT_DEV jtag_uart#define ALT_STDOUT_PRESENT#define ALT_STDERR "/dev/jtag_uart"#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"#define ALT_STDERR_BASE 0x00502890#define ALT_STDERR_DEV jtag_uart#define ALT_STDERR_PRESENT#define ALT_CPU_FREQ 50000000#define ALT_IRQ_BASE NULL/* * processor configuration * */#define NIOS2_CPU_IMPLEMENTATION "small"#define NIOS2_BIG_ENDIAN 0#define NIOS2_ICACHE_SIZE 4096#define NIOS2_DCACHE_SIZE 0#define NIOS2_ICACHE_LINE_SIZE 32#define NIOS2_ICACHE_LINE_SIZE_LOG2 5#define NIOS2_DCACHE_LINE_SIZE 0#define NIOS2_DCACHE_LINE_SIZE_LOG2 0#define NIOS2_FLUSHDA_SUPPORTED#define NIOS2_EXCEPTION_ADDR 0x01000020#define NIOS2_RESET_ADDR 0x00000000#define NIOS2_BREAK_ADDR 0x00501020#define NIOS2_HAS_DEBUG_STUB#define NIOS2_CPU_ID_SIZE 1#define NIOS2_CPU_ID_VALUE 0/* * A define for each class of peripheral * */#define __ALTERA_AVALON_JTAG_UART#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER#define __ALTERA_AVALON_PIO#define __ALTERA_AVALON_TIMER#define __ALTERA_AVALON_EPCS_FLASH_CONTROLLER#define __ALTERA_AVALON_ONCHIP_MEMORY2#define __ALTERA_AVALON_TRI_STATE_BRIDGE#define __ALTERA_AVALON_CFI_FLASH#define __ALTERA_AVALON_SYSID#define __GX_AVALON_ISP1362#define __OC_I2C_MASTER#define __SRAM_256X16BIT#define __GX_DM9000A/* * jtag_uart configuration * */#define JTAG_UART_NAME "/dev/jtag_uart"#define JTAG_UART_TYPE "altera_avalon_jtag_uart"#define JTAG_UART_BASE 0x00502890#define JTAG_UART_SPAN 8#define JTAG_UART_IRQ 1#define JTAG_UART_WRITE_DEPTH 64#define JTAG_UART_READ_DEPTH 64#define JTAG_UART_WRITE_THRESHOLD 8#define JTAG_UART_READ_THRESHOLD 8#define JTAG_UART_READ_CHAR_STREAM ""#define JTAG_UART_SHOWASCII 1#define JTAG_UART_READ_LE 0#define JTAG_UART_WRITE_LE 0#define JTAG_UART_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart/* * sdram1 configuration * */#define SDRAM1_NAME "/dev/sdram1"#define SDRAM1_TYPE "altera_avalon_new_sdram_controller"#define SDRAM1_BASE 0x01000000#define SDRAM1_SPAN 8388608#define SDRAM1_REGISTER_DATA_IN 1#define SDRAM1_SIM_MODEL_BASE 1#define SDRAM1_SDRAM_DATA_WIDTH 16#define SDRAM1_SDRAM_ADDR_WIDTH 12#define SDRAM1_SDRAM_ROW_WIDTH 12#define SDRAM1_SDRAM_COL_WIDTH 8#define SDRAM1_SDRAM_NUM_CHIPSELECTS 1#define SDRAM1_SDRAM_NUM_BANKS 4#define SDRAM1_REFRESH_PERIOD 15.625#define SDRAM1_POWERUP_DELAY 100.0#define SDRAM1_CAS_LATENCY 3#define SDRAM1_T_RFC 70.0#define SDRAM1_T_RP 20.0#define SDRAM1_T_MRD 3#define SDRAM1_T_RCD 20.0#define SDRAM1_T_AC 5.5#define SDRAM1_T_WR 14.0#define SDRAM1_INIT_REFRESH_COMMANDS 2#define SDRAM1_INIT_NOP_DELAY 0.0#define SDRAM1_SHARED_DATA 0#define SDRAM1_SDRAM_BANK_WIDTH 2#define SDRAM1_TRISTATE_BRIDGE_SLAVE ""#define SDRAM1_STARVATION_INDICATOR 0#define SDRAM1_IS_INITIALIZED 1#define ALT_MODULE_CLASS_sdram1 altera_avalon_new_sdram_controller/* * led_pio configuration * */#define LED_PIO_NAME "/dev/led_pio"#define LED_PIO_TYPE "altera_avalon_pio"#define LED_PIO_BASE 0x00502860#define LED_PIO_SPAN 16#define LED_PIO_DO_TEST_BENCH_WIRING 0#define LED_PIO_DRIVEN_SIM_VALUE 0#define LED_PIO_HAS_TRI 0#define LED_PIO_HAS_OUT 1#define LED_PIO_HAS_IN 0#define LED_PIO_CAPTURE 0#define LED_PIO_DATA_WIDTH 8#define LED_PIO_RESET_VALUE 0#define LED_PIO_EDGE_TYPE "NONE"#define LED_PIO_IRQ_TYPE "NONE"#define LED_PIO_BIT_CLEARING_EDGE_REGISTER 0#define LED_PIO_FREQ 50000000#define ALT_MODULE_CLASS_led_pio altera_avalon_pio/* * high_res_timer configuration * */#define HIGH_RES_TIMER_NAME "/dev/high_res_timer"#define HIGH_RES_TIMER_TYPE "altera_avalon_timer"#define HIGH_RES_TIMER_BASE 0x00502800#define HIGH_RES_TIMER_SPAN 32#define HIGH_RES_TIMER_IRQ 2#define HIGH_RES_TIMER_ALWAYS_RUN 0#define HIGH_RES_TIMER_FIXED_PERIOD 0#define HIGH_RES_TIMER_SNAPSHOT 1#define HIGH_RES_TIMER_PERIOD 20#define HIGH_RES_TIMER_PERIOD_UNITS "us"#define HIGH_RES_TIMER_RESET_OUTPUT 0#define HIGH_RES_TIMER_TIMEOUT_PULSE_OUTPUT 0#define HIGH_RES_TIMER_LOAD_VALUE 999#define HIGH_RES_TIMER_COUNTER_SIZE 32#define HIGH_RES_TIMER_MULT "1.0E-6"#define HIGH_RES_TIMER_TICKS_PER_SEC 50000#define HIGH_RES_TIMER_FREQ 50000000#define ALT_MODULE_CLASS_high_res_timer altera_avalon_timer/* * epcs_controller configuration * */#define EPCS_CONTROLLER_NAME "/dev/epcs_controller"#define EPCS_CONTROLLER_TYPE "altera_avalon_epcs_flash_controller"#define EPCS_CONTROLLER_BASE 0x00501800#define EPCS_CONTROLLER_SPAN 2048#define EPCS_CONTROLLER_IRQ 3#define EPCS_CONTROLLER_DATABITS 8#define EPCS_CONTROLLER_TARGETCLOCK 20#define EPCS_CONTROLLER_CLOCKUNITS "MHz"#define EPCS_CONTROLLER_CLOCKMULT 1000000#define EPCS_CONTROLLER_NUMSLAVES 1#define EPCS_CONTROLLER_ISMASTER 1#define EPCS_CONTROLLER_CLOCKPOLARITY 0#define EPCS_CONTROLLER_CLOCKPHASE 0#define EPCS_CONTROLLER_LSBFIRST 0#define EPCS_CONTROLLER_EXTRADELAY 0#define EPCS_CONTROLLER_TARGETSSDELAY 100#define EPCS_CONTROLLER_DELAYUNITS "us"#define EPCS_CONTROLLER_DELAYMULT "1e-006"#define EPCS_CONTROLLER_PREFIX "epcs_"#define EPCS_CONTROLLER_REGISTER_OFFSET 0x200#define EPCS_CONTROLLER_USE_ASMI_ATOM 1#define EPCS_CONTROLLER_CLOCKUNIT "kHz"#define EPCS_CONTROLLER_DELAYUNIT "us"#define ALT_MODULE_CLASS_epcs_controller altera_avalon_epcs_flash_controller/* * onchip_ram configuration * */#define ONCHIP_RAM_NAME "/dev/onchip_ram"#define ONCHIP_RAM_TYPE "altera_avalon_onchip_memory2"#define ONCHIP_RAM_BASE 0x00502000#define ONCHIP_RAM_SPAN 2048#define ONCHIP_RAM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0#define ONCHIP_RAM_RAM_BLOCK_TYPE "M4K"#define ONCHIP_RAM_INIT_CONTENTS_FILE "onchip_ram"#define ONCHIP_RAM_NON_DEFAULT_INIT_FILE_ENABLED 0#define ONCHIP_RAM_GUI_RAM_BLOCK_TYPE "Automatic"#define ONCHIP_RAM_WRITEABLE 1#define ONCHIP_RAM_DUAL_PORT 0#define ONCHIP_RAM_SIZE_VALUE 2048#define ONCHIP_RAM_SIZE_MULTIPLE 1#define ONCHIP_RAM_USE_SHALLOW_MEM_BLOCKS 0#define ONCHIP_RAM_INIT_MEM_CONTENT 1#define ONCHIP_RAM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0#define ONCHIP_RAM_INSTANCE_ID "NONE"#define ONCHIP_RAM_READ_DURING_WRITE_MODE "DONT_CARE"#define ONCHIP_RAM_IGNORE_AUTO_BLOCK_TYPE_ASSIGNMENT 1#define ONCHIP_RAM_CONTENTS_INFO ""#define ALT_MODULE_CLASS_onchip_ram altera_avalon_onchip_memory2/* * ext_bus configuration * */#define EXT_BUS_NAME "/dev/ext_bus"#define EXT_BUS_TYPE "altera_avalon_tri_state_bridge"#define ALT_MODULE_CLASS_ext_bus altera_avalon_tri_state_bridge/* * flash1 configuration * */#define FLASH1_NAME "/dev/flash1"#define FLASH1_TYPE "altera_avalon_cfi_flash"#define FLASH1_BASE 0x00000000#define FLASH1_SPAN 4194304#define FLASH1_SETUP_VALUE 40#define FLASH1_WAIT_VALUE 160#define FLASH1_HOLD_VALUE 40#define FLASH1_TIMING_UNITS "ns"#define FLASH1_UNIT_MULTIPLIER 1#define FLASH1_SIZE 4194304#define ALT_MODULE_CLASS_flash1 altera_avalon_cfi_flash/* * timer configuration * */#define TIMER_NAME "/dev/timer"#define TIMER_TYPE "altera_avalon_timer"#define TIMER_BASE 0x00502820#define TIMER_SPAN 32#define TIMER_IRQ 0#define TIMER_ALWAYS_RUN 0#define TIMER_FIXED_PERIOD 0#define TIMER_SNAPSHOT 1#define TIMER_PERIOD 10#define TIMER_PERIOD_UNITS "ms"#define TIMER_RESET_OUTPUT 0#define TIMER_TIMEOUT_PULSE_OUTPUT 0#define TIMER_LOAD_VALUE 499999#define TIMER_COUNTER_SIZE 32#define TIMER_MULT 0.0010#define TIMER_TICKS_PER_SEC 100#define TIMER_FREQ 50000000#define ALT_MODULE_CLASS_timer altera_avalon_timer/* * sysid configuration * */#define SYSID_NAME "/dev/sysid"#define SYSID_TYPE "altera_avalon_sysid"#define SYSID_BASE 0x00502898#define SYSID_SPAN 8#define SYSID_ID 992816754u#define SYSID_TIMESTAMP 1226459892u#define SYSID_REGENERATE_VALUES 0#define ALT_MODULE_CLASS_sysid altera_avalon_sysid/* * isp1362/avalon_slave_0 configuration * */#define ISP1362_AVALON_SLAVE_0_NAME "/dev/isp1362"#define ISP1362_AVALON_SLAVE_0_TYPE "gx_avalon_isp1362"#define ISP1362_AVALON_SLAVE_0_BASE 0x00502870#define ISP1362_AVALON_SLAVE_0_SPAN 16#define ISP1362_AVALON_SLAVE_0_IRQ 4#define ISP1362_AVALON_SLAVE_0_HDL_PARAMETERS ""#define ALT_MODULE_CLASS_isp1362 gx_avalon_isp1362/* * isp1362/avalon_slave_1 configuration * */#define ISP1362_AVALON_SLAVE_1_NAME "/dev/isp1362"#define ISP1362_AVALON_SLAVE_1_TYPE "gx_avalon_isp1362"#define ISP1362_AVALON_SLAVE_1_BASE 0x005028a8#define ISP1362_AVALON_SLAVE_1_SPAN 1#define ISP1362_AVALON_SLAVE_1_IRQ 5#define ISP1362_AVALON_SLAVE_1_HDL_PARAMETERS ""#define ALT_MODULE_CLASS_isp1362 gx_avalon_isp1362/* * i2c_master configuration * */#define I2C_MASTER_NAME "/dev/i2c_master"#define I2C_MASTER_TYPE "oc_i2c_master"#define I2C_MASTER_BASE 0x00502840#define I2C_MASTER_SPAN 32#define I2C_MASTER_IRQ 6#define ALT_MODULE_CLASS_i2c_master oc_i2c_master/* * button_pio configuration * */#define BUTTON_PIO_NAME "/dev/button_pio"#define BUTTON_PIO_TYPE "altera_avalon_pio"#define BUTTON_PIO_BASE 0x00502880#define BUTTON_PIO_SPAN 16#define BUTTON_PIO_IRQ 7#define BUTTON_PIO_DO_TEST_BENCH_WIRING 1#define BUTTON_PIO_DRIVEN_SIM_VALUE 0#define BUTTON_PIO_HAS_TRI 0#define BUTTON_PIO_HAS_OUT 0#define BUTTON_PIO_HAS_IN 1#define BUTTON_PIO_CAPTURE 1#define BUTTON_PIO_DATA_WIDTH 4#define BUTTON_PIO_RESET_VALUE 0#define BUTTON_PIO_EDGE_TYPE "FALLING"#define BUTTON_PIO_IRQ_TYPE "EDGE"#define BUTTON_PIO_BIT_CLEARING_EDGE_REGISTER 0#define BUTTON_PIO_FREQ 50000000#define ALT_MODULE_CLASS_button_pio altera_avalon_pio/* * sram1 configuration * */#define SRAM1_NAME "/dev/sram1"#define SRAM1_TYPE "sram_256x16bit"#define SRAM1_BASE 0x00480000#define SRAM1_SPAN 524288#define SRAM1_TERMINATED_PORTS ""#define ALT_MODULE_CLASS_sram1 sram_256x16bit/* * dm9000a configuration * */#define DM9000A_NAME "/dev/dm9000a"#define DM9000A_TYPE "gx_dm9000a"#define DM9000A_BASE 0x005028a0#define DM9000A_SPAN 8#define DM9000A_IRQ 8#define DM9000A_TERMINATED_PORTS ""#define ALT_MODULE_CLASS_dm9000a gx_dm9000a/* * system library configuration * */#define ALT_MAX_FD 32#define ALT_SYS_CLK TIMER#define ALT_TIMESTAMP_CLK none/* * Devices associated with code sections. * */#define ALT_TEXT_DEVICE       SDRAM1#define ALT_RODATA_DEVICE     SDRAM1#define ALT_RWDATA_DEVICE     SDRAM1#define ALT_EXCEPTIONS_DEVICE SDRAM1#define ALT_RESET_DEVICE      FLASH1#endif /* __SYSTEM_H_ */